ELF ( 4 4 X X ` 8 8
8 a0 ( 0 ` qcom,glymur qcom,glymur board-id ,default_process-glymur-1.0-adsp 6 soc @ ipcc
qcom,ipcc ipcc@3e02000 qcom,ipcc-protocol H L SMPROC a n y D ! " : ; < - . 7 8 @ ipcc@3e40000 qcom,ipcc-protocol H L SCOMPUTE_L0 a n N 0 ! "
- . @ ipcc@3e80000 qcom,ipcc-protocol H L SCOMPUTE_L1 a n 0 ! "
- . @ ipcc@3ec0000 qcom,ipcc-protocol H L SPERIPH a n D
! " , - . 7 8 @ ipcc_legacy@6888004 H @ ipcc_legacy_sdc qcom,ipcc-legacy L n 8 9 : ; @ timetick timer@68a2000 qcom,timetick H SystemTimer $ @ timer@68a3000 qcom,timetick H0 WakeUpTimer $ @ pinctrl@f100000 ! qcom,glymur-pinctrl qcom,pinctrl H n > O V B u $ } P 4summary directconn0 directconn1 directconn2 directconn3 directconn4 directconn5 D WGPIOINTADSP @ z qup0_se0_l0 h @ qup0_se0_l1 h @ qup0_se0_l2 h @ qup0_se0_l3 h @ qup0_se1_l0 h @ qup0_se1_l1 h @ qup0_se1_l2 h @ qup0_se1_l3 h @ qup0_se2_l0 h @ qup0_se2_l1 h @ qup0_se2_l2 h
@ qup0_se2_l3 h @ qup0_se2_l4 h @ qup0_se2_l5 h @ qup0_se2_l6 h @ qup0_se3_l0 h @ qup0_se3_l1 h
@ qup0_se3_l2 h @ qup0_se3_l3 h @ qup0_se3_l4 h @ qup0_se3_l5 h @ qup0_se3_l6 h @ qup0_se4_l0 h @ qup0_se4_l1 h @ qup0_se4_l2 h @ qup0_se4_l3 h @ qup0_se5_l0 h @ qup0_se5_l1 h @ qup0_se5_l2 h @ qup0_se5_l3 h @ qup0_se6_l0 h @ qup0_se6_l1 h @ qup0_se6_l2 h @ qup0_se6_l3 h @ qup0_se7_l0 h @ qup0_se7_l1 h @ qup0_se7_l2 h @ qup0_se7_l3 h
@ qup1_se0_l0 h @ qup1_se0_l1 h ! @ qup1_se0_l2 h " @ qup1_se0_l3 h # @ qup1_se1_l0 h $ @ qup1_se1_l1 h % @ qup1_se1_l2 h & @ qup1_se1_l3 h ' @ qup1_se2_l0 h ( @ qup1_se2_l1 h ) @ qup1_se2_l2 h * @ qup1_se2_l3 h + @ qup1_se2_l4 h 1 @ qup1_se2_l5 h 2 @ qup1_se2_l6 h 3 @ qup1_se3_l0 h , @ qup1_se3_l1 h - @ qup1_se3_l2 h . @ qup1_se3_l3 h / @ qup1_se3_l4 h ! @ qup1_se3_l5 h " @ qup1_se3_l6 h # @ qup1_se4_l0 h 0 @ qup1_se4_l1 h 1 @ qup1_se4_l2 h 2 @ qup1_se4_l3 h 3 @ qup1_se5_l0 h 4 @ qup1_se5_l1 h 5 @ qup1_se5_l2 h 6 @ qup1_se5_l3 h 7 @ qup1_se6_l0 h 8 @ qup1_se6_l1 h 9 @ qup1_se6_l2 h : @ qup1_se6_l3 h ; @ qup1_se7_l0 h 6 @ qup1_se7_l1 h 7 @ qup1_se7_l2 h 4 @ qup1_se7_l3 h 5 @ qup2_se0_l0 h @ @ qup2_se0_l1 h A @ qup2_se0_l2 h B @ qup2_se0_l3 h C @ qup2_se1_l0 h D @ qup2_se1_l1 h E @ qup2_se1_l2 h F @ qup2_se1_l3 h G @ qup2_se2_l0 h H @ qup2_se2_l1 h I @ qup2_se2_l2 h J @ qup2_se2_l3 h K @ qup2_se2_l4 h Q @ qup2_se2_l5 h R @ qup2_se2_l6 h S @ qup2_se3_l0 h L @ qup2_se3_l1 h M @ qup2_se3_l2 h N @ qup2_se3_l3 h O @ qup2_se3_l4 h A @ qup2_se3_l5 h B @ qup2_se3_l6 h C @ qup2_se4_l0 h P @ qup2_se4_l1 h Q @ qup2_se4_l2 h R @ qup2_se4_l3 h S @ qup2_se5_l0 h T @ qup2_se5_l1 h U @ qup2_se5_l2 h V @ qup2_se5_l3 h W @ qup2_se6_l0 h X @ qup2_se6_l1 h Y @ qup2_se6_l2 h Z @ qup2_se6_l3 h [ @ qup2_se7_l0 h P @ qup2_se7_l1 h Q @ qup2_se7_l2 h R @ qup2_se7_l3 h S @ qup3_se0_l0 h @ qup3_se0_l1 h @ qup3_se0_l2 h @ qup3_se0_l3 h @ qup3_se0_l4 h @ qup3_se0_l5 h @ qup3_se0_l6 h @ qup3_se0_l7 h @ qup3_se1_l0 h ( @ qup3_se1_l1 h ) @ qup3_se1_l2 h * @ qup3_se1_l3 h + @ qup3_se1_l4 h 1 @ qup3_se1_l5 h 2 @ qup3_se1_l6 h 3 @ qup3_se1_l7 h 0 @ GPIO_config_active l @ { GPIO_config_idle l @ | GPIO_config_sleep l @ } GPIO_config_wake l
@ ~ pinctrl@7760000 ! qcom,glymur-pinctrl qcom,pinctrl Hv s l E E E E E E E E E E E E E E E E E E E E E E E E E E E @ slimbus_clk h @ slimbus_data h @ slimbus_default_gpio_cfg l ! ! @ y pinctrl@75C0000 ! qcom,glymur-pinctrl qcom,pinctrl H\ - a a E E Q Q E E a a E E E E I E Q Q E E E E E E E E E E E E E E E E E E E E Q Q E E E E E @
ssc_gpio_10_clk h
@ ssc_gpio_11_clk h @ ssc_gpio_12_clk h @
ssc_gpio_13_clk h
@ ssc_gpio_18_clk h @ ssc_gpio_19_clk h @ ssc_gpio_24_clk h @ ssc_gpio_25_clk h @ ssc_gpio_26_clk_reserved h @ ssc_gpio_27_clk_reserved h @ ssc_gpio_28_clk_reserved h @ ssc_gpio_29_clk_reserved h @ ssc_gpio_30_clk_reserved h @ ssc_gpio_31_clk_reserved h @ ssc_gpio_34_clk_reserved h " @ ssc_gpio_35_clk_reserved h # @ ssc_gpio_6_clk h @ ssc_gpio_7_clk h @ ssc_qupv3_se0_0 h @ ssc_qupv3_se0_1 h @ ssc_qupv3_se10_0 h @ ! ssc_qupv3_se10_1 h @ " ssc_qupv3_se10_2 h @ # ssc_qupv3_se10_3 h @ $ ssc_qupv3_se11_0_reserved h @ ssc_qupv3_se11_1_reserved h @ ssc_qupv3_se11_2_reserved h @ ssc_qupv3_se11_3_reserved h @ ssc_qupv3_se12_0_reserved h @ ! ssc_qupv3_se12_1_reserved h @ " ssc_qupv3_se13_0_reserved h @ # ssc_qupv3_se13_1_reserved h ! @ $ ssc_qupv3_se13_2_reserved h " @ % ssc_qupv3_se13_3_reserved h # @ & ssc_qupv3_se14_0_reserved h $ @ ' ssc_qupv3_se14_1_reserved h % @ ( ssc_qupv3_se1_0 h @ ssc_qupv3_se1_1 h @ ssc_qupv3_se1_2_reserved h @ ) ssc_qupv3_se1_3_reserved h @ * ssc_qupv3_se2_0 h @ ssc_qupv3_se2_1 h @
ssc_qupv3_se2_2 h @ ssc_qupv3_se2_3 h @ ssc_qupv3_se2_4 h @ + ssc_qupv3_se2_5 h @ , ssc_qupv3_se3_0 h @
ssc_qupv3_se3_1 h @ ssc_qupv3_se4_0 h
@ ssc_qupv3_se4_1 h @ ssc_qupv3_se4_2 h @ ssc_qupv3_se4_3 h
@ ssc_qupv3_se4_4 h @ - ssc_qupv3_se4_5 h @ . ssc_qupv3_se5_0 h @ ssc_qupv3_se5_1 h @ ssc_qupv3_se5_2 h @ ssc_qupv3_se5_3 h @ ssc_qupv3_se6_0 h @ ssc_qupv3_se6_1 h @ ssc_qupv3_se6_2 h @ ssc_qupv3_se6_3 h @ ssc_qupv3_se7_0 h @ ssc_qupv3_se7_1 h @ ssc_qupv3_se7_2 h @ ssc_qupv3_se7_3 h @ ssc_qupv3_se8_0 h @ ssc_qupv3_se8_1 h @ ssc_qupv3_se9_0_reserved h @ / ssc_qupv3_se9_1_reserved h @ 0 qup_ssc0_se0_i2c_active l @ 1 qup_ssc0_se0_i2c_sleep l @ 2 qup_ssc0_se0_i3c_active l
@ 3 qup_ssc0_se0_i3c_sleep l ! ! @ 4 qup_ssc0_se0_i3c_ibi_active l
@ 5 qup_ssc0_se0_i3c_ibi_sleep l ! ! @ 6 qup_ssc0_se1_i2c_active l @ 7 qup_ssc0_se1_i2c_sleep l @ 8 qup_ssc0_se1_i3c_active l
@ 9 qup_ssc0_se1_i3c_sleep l ! ! @ : qup_ssc0_se1_i3c_ibi_active l
@ ; qup_ssc0_se1_i3c_ibi_sleep l ! ! @ < qup_ssc0_se2_i2c_active l
@ = qup_ssc0_se2_i2c_sleep l
@ > qup_ssc0_se2_i3c_active l
@ ? qup_ssc0_se2_i3c_sleep l !
! @ @ qup_ssc0_se2_i3c_ibi_active l
@ A qup_ssc0_se2_i3c_ibi_sleep l !
! @ B qup_ssc0_se2_spi_active l X
X X X @ C qup_ssc0_se2_spi_sleep l !
! ! ! @ D qup_ssc0_se2_uart_active l
@ E qup_ssc0_se2_uart_sleep l
@ F qup_ssc0_se3_i2c_active l
@ G qup_ssc0_se3_i2c_sleep l
@ H qup_ssc0_se3_i3c_active l
@ I qup_ssc0_se3_i3c_sleep l
! ! @ J qup_ssc0_se3_i3c_ibi_active l
@ K qup_ssc0_se3_i3c_ibi_sleep l
! ! @ L qup_ssc0_se4_i2c_active l @ M qup_ssc0_se4_i2c_sleep l @ N qup_ssc0_se4_spi_active l X X X X @ O qup_ssc0_se4_spi_sleep l ! ! ! ! @ P qup_ssc0_se4_uart_active l @ Q qup_ssc0_se4_uart_sleep l @ R qup_ssc0_se5_i2c_active l @ S qup_ssc0_se5_i2c_sleep l @ T qup_ssc0_se5_i3c_active l
@ U qup_ssc0_se5_i3c_sleep l ! ! @ V qup_ssc0_se5_i3c_ibi_active l
@ W qup_ssc0_se5_i3c_ibi_sleep l ! ! @ X qup_ssc0_se5_spi_active l X X X X @ Y qup_ssc0_se5_spi_sleep l ! ! ! ! @ Z qup_ssc0_se5_uart_active l @ [ qup_ssc0_se5_uart_sleep l @ \ qup_ssc0_se6_i2c_active l @ ] qup_ssc0_se6_i2c_sleep l @ ^ qup_ssc0_se6_i3c_active l
@ _ qup_ssc0_se6_i3c_sleep l ! ! @ ` qup_ssc0_se6_i3c_ibi_active l
@ a qup_ssc0_se6_i3c_ibi_sleep l ! ! @ b qup_ssc0_se6_spi_active l X X X X @ c qup_ssc0_se6_spi_sleep l ! ! ! ! @ d qup_ssc0_se6_uart_active l @ e qup_ssc0_se6_uart_sleep l @ f qup_ssc0_se7_i2c_active l @ g qup_ssc0_se7_i2c_sleep l @ h qup_ssc0_se7_spi_active l X X X X @ i qup_ssc0_se7_spi_sleep l ! ! ! ! @ j qup_ssc0_se7_uart_active l @ k qup_ssc0_se7_uart_sleep l @ l qup_ssc0_se8_i2c_active l @ m qup_ssc0_se8_i2c_sleep l @ n qup_ssc0_se8_i3c_active l
@ o qup_ssc0_se8_i3c_sleep l ! ! @ p qup_ssc0_se8_i3c_ibi_active l
@ q qup_ssc0_se8_i3c_ibi_sleep l ! ! @ r qup_ssc0_se10_i2c_active l ! " @ s qup_ssc0_se10_i2c_sleep l ! " @ t qup_ssc0_se10_spi_active l !X "X #X $X @ u qup_ssc0_se10_spi_sleep l ! ! " ! # ! $ ! @ v qup_ssc0_se10_uart_active l ! " # $ @ w qup_ssc0_se10_uart_sleep l ! " # $ @ x vdd_mxa qcom,rpmh-arc-regulator /vcs/vdd_mxa /vcs/vdd_mx mx.lvl $ @ 1 vdd_mxc qcom,rpmh-arc-regulator
/vcs/vdd_mxc mxc.lvl $ @ 2 vdd_cx qcom,rpmh-arc-regulator /vcs/vdd_cx cx.lvl $ @ 3 vdd_lpi_mx qcom,rpmh-arc-regulator /vcs/vdd_lpi_mx /vcs/vdd_ssc_mx lmx.lvl $? @ 4 vdd_lpi_cx qcom,rpmh-arc-regulator ! /vcs/vdd_lpi_cx /vcs/vdd_ssc_int lcx.lvl $? @ 5 clock-controller@100000 qcom,gcc-glymur qcom,cc-glymur H 0 @ P ` p 0 @ / / 0GCC_GPLL0_CM_PLL_TAYCAN_COMMON GCC_GPLL1_CM_PLL_TAYCAN_COMMON GCC_GPLL2_CM_PLL_TAYCAN_COMMON GCC_GPLL3_CM_PLL_TAYCAN_COMMON GCC_GPLL4_CM_PLL_TAYCAN_COMMON GCC_GPLL5_CM_PLL_TAYCAN_COMMON GCC_GPLL6_CM_PLL_TAYCAN_COMMON GCC_GPLL7_CM_PLL_TAYCAN_COMMON GCC_GPLL8_CM_PLL_TAYCAN_COMMON GCC_GPLL9_CM_PLL_TAYCAN_COMMON GCC_GPLL10_CM_PLL_ZONDA_COMMON GCC_GPLL11_CM_PLL_ZONDA_COMMON GCC_GPLL12_CM_PLL_ZONDA_COMMON GCC_GPLL13_CM_PLL_ZONDA_COMMON GCC_GPLL14_CM_PLL_TAYCAN_COMMON GCC_GPLL15_CM_PLL_TAYCAN_COMMON GCC_GPLL16_CM_PLL_TAYCAN_COMMON GCC_GPLL17_CM_PLL_TAYCAN_COMMON GCC_GPLL18_CM_PLL_TAYCAN_COMMON GCC_GPLL19_CM_PLL_TAYCAN_COMMON GCC_JBIST_CM_PLL_JBIST4_COMMON GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_RPUQ11_512_CL36L12_LE GCC_RPU_XPU4 : @ 6 clock-controller@1f40000 ( qcom,lpass_aon_cc-glymur qcom,cc-glymur P H ` p & < 0TCSR_TCSR_REGS LPASS_QDSP6SS_QDSP6SS_PUB LPASS_QDSP6SS_QDSP6SS_QDSP6SSV81_CORE_CC_SWI LPASS_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON LPASS_QDSP6SS_QDSP6SSV81_CORE_CC_REG LPASS_AON_CC_PLL_CM_PLL_TAYCAN_COMMON LPASS_AON_CC_AHB2PHY_SWMAN LPASS_AON_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_CC_LPASS_AON_CC_REG LPASS_LPI_TCM_REG : @ / clock-controller@7700000 + qcom,lpass_aon_mx_cc-glymur qcom,cc-glymur Hp p` pp p 0LPASS_AON_MX_CC_RO_PLL_CM_PLL_PONGO_COMMON LPASS_AON_MX_CC_AHB2PHY_SWMAN LPASS_AON_MX_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_MX_CC_LPASS_AON_MX_CC_REG : @ 7 clock-controller@6bc0000 * qcom,lpass_audio_cc-glymur qcom,cc-glymur 0 H ` p 0LPASS_AUDIO_CC_PLL_CM_PLL_ZONDA_COMMON LPASS_AUDIO_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_AUDIO_CC_LCC_PLL_CM_PLL_JBIST4_COMMON LPASS_AUDIO_CC_AHB2PHY_SWMAN LPASS_AUDIO_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AUDIO_CC_LPASS_AUDIO_CC_REG : @ 8 clock-controller@7b00000 ) qcom,lpass_core_cc-glymur qcom,cc-glymur 0 H ` p 0 0LPASS_LPASS_CORE_CC_DIG_PLL_LPASS_CORE_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_LPASS_CORE_CC_REG LPASS_HW_AF_CORE LPASS_CORE_GDSC : @ 9 clock-controller@6e40000 * qcom,lpass_lpmla_cc-glymur qcom,cc-glymur H ` p @ 0LPASS_LPMLA_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPMLA_CC_AHB2PHY_SWMAN LPASS_LPMLA_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPMLA_CC_LPASS_LPMLA_CC_REG : @ : clock-controller@7a00000 qcom,scc-glymur qcom,cc-glymur H 0SSC_SCC_SCC_SCC_REG : @ 0 cesta@7213000 ' qcom,lpass_cesta-glymur qcom,cc-glymur ( H!0 !4 !8 !X !_ @ 0LPASS_CRMB LPASS_CRMB_PT LPASS_CRMC LPASS_CRMV LPASS_CRM_COMMON @ ; glink qcom,glink G proc-info W xport-smem-config edge-01 \ h @ r { N xport-qmp-config edge-01 aop_adsp \ { @ ipc_router qcom,ipc_router proc-info adsp devcfg-glink-xals edge-01 SMEM apss IPCRTR ' / 8 C smp2p qcom,smp2p proc-info K S Z smp2p-interrupts intr-01 f R k intr-02 f R k smem
qcom,smem
oCORE_TOP_CSR 0
@
@ cxstmtrace@16000000 qcom,stmtrace H lpistmtrace@7100000 qcom,stmtrace H @ cxstmcfg@10002000 qcom,stmcfg H lpistmcfg@11c43000 qcom,stmcfg H0 cxetb@11c05000 qcom,tmc HP lpietb@11c45000 qcom,tmc HP tpdm@11c46000
qcom,tpdm H` tpdm_31 % tpdm@11c52000
qcom,tpdm H tpdm_62 & tpdm@11c54000
qcom,tpdm H@ tpdm_22 ' tpdm@11c34000
qcom,tpdm H@ tpdm_50 ( tpdm@11c3c000
qcom,tpdm H tpdm_8 ) qdss 0 L L !_!_ - * 8 H + , * _ + , * z + , * * , * , + , * - * , * , * , * , * $ , * - + , * < + , * cti@11c35000 qcom,cti ( Kddrss_lpi_slice0cti_cti_qc_cti_extended HP cti@11c42000 qcom,cti $ Klpass_lpi_cti_sdc_2_cti_sdc_2_cscti H cti@11c4b000 qcom,cti & Klpass_lpi_qdsp6_qdsp6ss_qdsp6ss_cscti Hİ cti@11c51000 qcom,cti " Klpass_lpi_cti_3_cti_3_qc_cti_core H cti@11c41000 qcom,cti " Klpass_lpi_cti_1_cti_1_qc_cti_core H cti@11c3d000 qcom,cti ( Kddrss_lpi_slice1cti_cti_qc_cti_extended H qdss_lpi_csr@6ee0000 qcom,qdss_lpi_csr H funnel@10041000
qcom,tfunnel H @ - funnel@11c44000
qcom,tfunnel H@ @ , funnel@11c50000
qcom,tfunnel H @ + funnel@11c04000
qcom,tfunnel H@ @ * tnoc@11c31000
qcom,tnoc T ( H * ) \port_ddrss_lpi_slice0ddrss_lpi_trace_noc @ ( tnoc@11c39000
qcom,tnoc T ) HÐ 9 ) \port_ddrss_lpi_slice0ddrss_lpi_trace_noc @ ) tpda@11c47000
qcom,tpda Hp mtpda_26 w port_lpass_lpi_dl_tpda @ % tpda@11c53000
qcom,tpda H0 mtpda_55 7 w port_lpass_lpi_crm_dl_tpda @ & tpda@11c55000
qcom,tpda HP mtpda_56 8 w port_lpass_lpi_audio_hm_dl_tpda @ ' systemcache@20400000 qcom,systemcache x H @ ` ! ! ! ! " " " " # # # # ( 0llcc_bcast_or_base llcc_bcast_and_base llcc0_base llcc1_base llcc2_base llcc3_base llcc4_base llcc5_base llcc6_base llcc7_base llcc8_base llcc9_base llcc10_base llcc11_base ddrss_regs_base @ @ llc-island qcom,llc-island islands ˀ island@c,80000000 H X subsys_instance qcom,subsys_instance spmi-bus@c400000 qcom,spmi-pmic-arb H @ @ < pmic@0 qcom,spmi-pmic H @ = spmi-vadc@92 qcom,spmi-vadc H . vadc_ch_cfg VPH_PWR VPH_PWR % / 6 @ K S ] e vadc-avg-ch gpio-map therm_table @ . therm_tb1 j q @x - $ R Ȩ (l m % 1 z % * 5` / 4 9 > C i H V M G| R ;` W 18 \ )h a " f L k p " u z
\
vadctm_meas_cfg w VPH_PWR VPH_PWR K S e ' spmi-bus@c436000 qcom,spmi-pmic-arb H @ @ > spmi-bus@c447000 qcom,spmi-pmic-arb H @ @ ? ssc_qup_fw_cfg qcom,qupfw-controller ssc_qup_0 se0_cfg P se1_cfg @ Q se2_cfg R se3_cfg S se4_cfg se5_cfg @ T se6_cfg U se7_cfg se8_cfg
V se10_cfg
ibi_ssc_0_cfg@7500000 qcom,ibi-controller HP T
G ! #ok @ @ ibi_ssc_1_cfg@7510000 qcom,ibi-controller HQ T
f #ok @ A ibi_ssc_2_cfg@7520000 qcom,ibi-controller HR T
#ok @ B ibi_ssc_3_cfg@7530000 qcom,ibi-controller HS T
#ok @ C ibi_ssc_4_cfg@7540000 qcom,ibi-controller HT T
#ok @ D ibi_ssc_5_cfg@7550000 qcom,ibi-controller HU T
#ok @ E ibi_ssc_6_cfg@7560000 qcom,ibi-controller HV T
#ok @ F ssc_pwr_domains qcom,ssc-pwr-domain-controller *ssc_gdsc 6 /@H SSC_QUP_0@7900000 qcom,sscqup-controller H *core2x core s-ahb m-ahb 6 0Sd 0d4 0v 0^, = D V mр |
#ok SSC_QUP_0_SE_0 qcom,se-controller ǘ
+ 1 ; H \ *se-clk 6 0H J oi2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep } 1 2 3 4 5 6 #ok SSC_QUP_0_SE_1 qcom,se-controller @ ǘ
, p 1 ; H \ *se-clk 6 0 Ǟ J oi2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep } 7 8 9 : ; < #ok SSC_QUP_0_SE_2 qcom,se-controller Ǟ
- 1 ; H \ *se-clk 6 0~E: x oi2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep } = > ? @ A B C D E F #ok SSC_QUP_0_SE_3 qcom,se-controller ǘ
. 1 ; H \ *se-clk 6 0 w J oi2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep } G H I J K L #ok SSC_QUP_0_SE_4 qcom,se-controller
/ 1 ; H \ *se-clk 6 0*̉ D oi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep } M N O P Q R #ok SSC_QUP_0_SE_5 qcom,se-controller @ Ǟ
0 w 1 ; H \ *se-clk 6 0 x oi2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep } S T U V W X Y Z [ \ #ok SSC_QUP_0_SE_6 qcom,se-controller Ǟ
1 1 ; H \ *se-clk 6 0 x oi2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep } ] ^ _ ` a b c d e f #ok SSC_QUP_0_SE_7 qcom,se-controller
* 1 ; H \ *se-clk 6 0O D oi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep } g h i j k l #ok SSC_QUP_0_SE_8 qcom,se-controller ǘ
) 1 ; H \ *se-clk 6 0pP J oi2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep } m n o p q r #ok SSC_QUP_0_SE_10 qcom,se-controller
1 ; H \ *se-clk 6 0 D oi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep } s t u v w x #ok qup_tcsr_info qcom,quptcsr-controller tcsr_cfg0 k
tcsr_cfg1
gsi_info qcom,gsi-controller gsi_qup_0 @ !T + < Z @ E U ^ e gsi_qup_1 @ !h + < [ @ E U ^ e gsi_qup_2 @ ! + < d @ E U ^ e gsi_qup_3 @ !p + < j @ E U ^ e gsi_ssc_qup_0 @ ! + < @ E ! " # $ % & ' ( U ^ e SlimbusBSP qcom,smbus-controller j uSLIMBUS 0 LPASS @ 2 B oslimbus-default } y
sb_0_DeviceProps
0
" sb_1_DeviceProps
0
" sb_2_DeviceProps
0
" sb_3_DeviceProps
0
" sb_4_DeviceProps
0
" sb_5_DeviceProps
" sb_6_DeviceProps
" slimbus_gen_config_1
0
ALPASS
O/vcs/vdd_lpi_cx
[
e
x
w0
svs_npa_str
0 C a x sbMmpmRegParam j slimbus * 7 E sbLpmMmpmRegParam { slimbus * 7 E kernel_test_devices@0 H n interrupt-controller@10140000 test,interrupt-control H T i @ device1@f101000 qcom,test,singleton zDevice region mapping with name H device1 0test_reg_singleton ] 4int1 device2@1011000 qcom,test,singleton ! zDevice region mapping with index device2 H ^ 4int2 device3@0 qcom,test,singleton zDevice with no region mapping device3 H _ 4int3 device4@1 qcom,test,not_compatible zDevice not compatible device4 H `
4zero int4 device5@1010000 qcom,test,non_singleton zDevice region mapping with name H device5 0test_reg_non_singleton sw @ G core boot l mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config debugtrace qcom,debugtrace debugtools version_tbl qcom,image_version_tbl_idx eic qcom,eic Z err_qdi
qcom,err_qdi P
pd_mon audio_process qcom,pd_mon_user_process_config
/ramfs/audio_lpai.mbn 3
0/rfs/root/vendor/firmware_mnt/image/audio_lpai.mbn
Faudio_process
N
b
uaudio_pd charger_process qcom,pd_mon_user_process_config
0
Fcharger_process
N
b
ucharger_pd qsh_process qcom,pd_mon_user_process_config
/ramfs/qsh.mbn ,
0/rfs/root/vendor/firmware_mnt/image/qsh.mbn
Fqsh_process
N
b
usensor_pd ois_process qcom,pd_mon_user_process_config
/ramfs/ois_lpai.mbn ,
0/rfs/root/vendor/firmware_mnt/image/ois.mbn
Fois_process
N
b
uois_pd pd_mon_restart qcom,pd_mon_restart
rcinit qcom,rcinit_cfg rcinit_config_spinor
d
u0
3 O k rcinit_config
!4
3 O k tms_diag qcom,tms_diag 0 products pram_mgr qcom,pram_mgr SSC_PRAM pram_partition QMP QMP m SENSORS SENSORS m BUSES BUSES m GPI GPI m ( WIGIG WIGIG m BUSES_DEBUG BUSES_DEBUG m CAMERA_OIS CAMERA_OIS m SENSORS_OIS SENSORS_OIS m sdcloader qcom,sdcloader sdc_params < * 8 Fa sdc_physpool P f |'P test socinfra gpio-pins z oactive idle sleep wake } { | } ~ icb adsp uart_sw qcom,icb_bw_vote_sw / mem high-spd low-spd idle " systemcache qcom,systemcache-sw @ ) - . llc-lpi-dump qcom,llc-lpi-dump J 1QSH_ISLAND_POOL SSC_ISLAND_POOL QSHTECH_ISLAND_POOL CAM_LLCC_ISLAND1_POOL diag qcom,adsp_core_diagcfg diagcfg_cmd < O h * = U Z = Y n
" ) B _ v ! diagcfg_param @ - @ T h |
. J b w 2 @ * 9 P ^ } < ( BK [ s d
) ? X t / F _ @ | < Z QURTOS_ISLAND_POOL QURTOS_ISLAND_POOL diagcfg_early_log / _ C Y diagcfg_f3_trace q qdsp_pm config qcom,config_data lpassRegRange m l2ConfigRegRange m cores-array core0 e
7 > M core1 f
7 M core2 g
7 " M core3 h
7 M core4 i
7 M core5 j
X 7 M core6 l
7 ! M core7 m
S 7 M core8 o
7 . M core9 {
7 2 M core10 r
7 + M core11 v
7 / M core12 w
] 7 M core13 y
7 1 M core14 z
7 0 M core15 |
n o 7 6 7 M core16
j 7 M core17
m 7 M core18
k 7 M core19
l 7 5 M memories-array memory0 Z memory1 Z clocks-array clock0 ` f n z/clk/cpu clock1 ` f n zlpass_core_cc_core_clk clock2 ` f n zlpass_audio_cc_bus_clk clock3 ` f n zlpass_aon_cc_aon_h_clk clock4 ` 6 f n zlpass_aon_cc_lpi_noc_ls_clk clock5 ` 7 f n zlpass_aon_cc_lpi_noc_hs_clk clock6 ` f n zlpass_audio_cc_slimbus_core_clk clock7 ` f n zlpass_core_cc_lpm_core_clk clock8 ` f n zlpass_core_cc_lpm_mem0_core_clk clock9 ` f n zlpass_audio_cc_codec_mem_clk clock10 ` f n zlpass_audio_cc_codec_mem0_clk clock11 ` f n zlpass_audio_cc_codec_mem1_clk clock12 ` f n zlpass_audio_cc_codec_mem2_clk clock13 ` f n zlpass_audio_cc_codec_mem3_clk clock14 ` f n zlpass_aon_mx_cc_va_mem0_clk clock15 ` f n zlpass_aon_mx_cc_va_mem1_clk clock16 ` f n $ zlpass_core_cc_sysnoc_mport_core_clk clock17 ` f n zlpass_audio_cc_bus_timeout_clk clock18 ` C f n ( zlpass_aon_cc_lpass_0_lpmla_ahb_odsc_clk clock19 ` D f n ( zlpass_aon_cc_lpass_1_lpmla_ahb_odsc_clk clock20 ` f n # zlpass_core_cc_sysnoc_sway_core_clk clock21 ` ? f n zscc_ccd_ahb2ahb_m_clk clock22 ` @ f n zscc_ccd_ahb2ahb_s_clk clock23 ` A f n zscc_ahb2ahb_s_clk clock24 ` B f n zlpass_aon_mx_cc_ibi_clk clock25 ` S f n zlpass_core_cc_resampler_clk clock26 ` X f n zlpass_audio_cc_slimbus_clk clock27 ` Z f n zlpass_core_cc_avsync_stc_clk clock28 ` [ f n zlpass_core_cc_avsync_atime_clk clock29 ` ] f n zlpass_core_cc_hw_af_clk clock30 ` ^ f n zlpass_core_cc_hw_af_noc_clk clock31 ` n f n ! zlpass_lpmla_cc_lpass_0_lpmla_clk clock32 ` o f n ! zlpass_lpmla_cc_lpass_1_lpmla_clk clock33 ` t f n zlpass_aon_cc_enpu_scheduler_clk clock34 ` j f n zlpass_aon_cc_sdc_proc_fclk_clk clock35 ` m f n zscc_ccd_clk clock36 ` l f n
zscc_smem_clk busport-array busPort0 busPort1 @ busPort2 @ @ busPort3 A @ busPort4 B @ busPort5 C @ busPort6 D @ busPort7 busPort8 busPort9 busPort10 busPort11 @ busPort12 busPort13
busPort14 @ ^ busPort15 busPort16 @ 1 busPort17 @ 1 busPort18 busPort19 busPort20 $ busPort21 $ busPort22 $ busPort23 $ busPort24 ! $ busPort25 " $ busPort26 $ $ busPort27 % $ busPort28 ' ' $ busPort29 ( $ busPort30 + $ busPort31 1 $ busPort32 0 $ busPort33 . $ busPort34 2 $ busPort35 / $ busPort36 6 C $ busPort37 7 D $ busPort38 5 l 5 busPort39 > > extroute-array extBusRoute0 % extBusRoute1 @ ( extBusRoute2 % extBusRoute3 A ( extBusRoute4 % extBusRoute5 B ( extBusRoute6 % extBusRoute7 C ( extBusRoute8 % extBusRoute9 D ( mipsroute-array mipsBwRoute0 % mipsBwRoute1 @ ( pwrDomain-array pwrDomain0 /core/cpu/latency `
. pwrDomain1 ! lpass_core_cc_lpass_core_hm_gdsc `
. pwrDomain2 ! lpass_aon_cc_lpass_audio_hm_gdsc `
. pwrDomain3 `
. pwrDomain4 lpass_aon_cc_lpass_ssc_gdsc `
. cestaBw-array client0 = G Nlpass path0 Z h 5 cestaClk-array clk0 ` j zlpass_aon_cc_sdc_proc_fclk_clk cestaPwrDomain-array pwrDomain0 lpass_aon_cc_lpass_ssc_gdsc features-array feature0 u feature1 u feature2 u feature3 u feature4 u feature5 u feature6 u feature7 u feature8 u feature9 u feature10 u 5 feature11 u / feature12 u feature13 u feature14 u $=X feature15 u ' feature16 u feature17 u feature18 u feature19 u feature20 u feature21 u feature22 u feature23 u feature24 u feature25 u feature26 u feature27 u feature28 u feature29 u feature30 u feature31 u feature32 u feature33 u feature34 u feature35 u feature36 u feature37 u config_arch qcom,config_arch compensatedDdrBwTable 0 y rp 0 0 ܓ X 0 t 2 0 U 2 0 &6 0 , s 0 2 0 8ـ 0 > 0 adspsnocVoteTable 8 y ' 8 ' 8 ܓ X X ' 8 t 2 ' 8 U e ' 8 &6 O ' 8 , ' 8 2 ' 8 8ـ U ' 8 > * ' 8 ' compensatedLecDdrBwTable 0 y X 0 2 0 0 ׄ s 0 e 0 adspLecsnocVoteTable 8 y X 8 2 8 O 8 ׄ 8 e U 8 compensatedMlDdrBwTable 0 y rp X 0 kI 0 Н 2 0 8 0 GW s 0 n! 0 adspMlsnocVoteTable 8 y X 8 kI 8 Н 2 8 8 O 8 GW 8 n! U 8 adspToLpiNocFreqTable y 0 $ $ ' 3
v =P 5 M O bkP j mlToLpiNocFreqTable y$ $ O ' RH
v 5 & O 0 j __symbols__ /soc /soc/ipcc/ipcc@3e02000 /soc/ipcc/ipcc@3e40000 /soc/ipcc/ipcc@3e80000 /soc/ipcc/ipcc@3ec0000 /soc/ipcc_legacy@6888004 /soc/timetick/timer@68a2000 /soc/timetick/timer@68a3000 &/soc/pinctrl@f100000 ! +/soc/pinctrl@f100000/qup0_se0_l0 ! 7/soc/pinctrl@f100000/qup0_se0_l1 ! C/soc/pinctrl@f100000/qup0_se0_l2 ! O/soc/pinctrl@f100000/qup0_se0_l3 ! [/soc/pinctrl@f100000/qup0_se1_l0 ! g/soc/pinctrl@f100000/qup0_se1_l1 ! s/soc/pinctrl@f100000/qup0_se1_l2 ! /soc/pinctrl@f100000/qup0_se1_l3 ! /soc/pinctrl@f100000/qup0_se2_l0 ! /soc/pinctrl@f100000/qup0_se2_l1 ! /soc/pinctrl@f100000/qup0_se2_l2 ! /soc/pinctrl@f100000/qup0_se2_l3 ! /soc/pinctrl@f100000/qup0_se2_l4 ! /soc/pinctrl@f100000/qup0_se2_l5 ! /soc/pinctrl@f100000/qup0_se2_l6 ! /soc/pinctrl@f100000/qup0_se3_l0 ! /soc/pinctrl@f100000/qup0_se3_l1 ! /soc/pinctrl@f100000/qup0_se3_l2 ! /soc/pinctrl@f100000/qup0_se3_l3 ! /soc/pinctrl@f100000/qup0_se3_l4 ! /soc/pinctrl@f100000/qup0_se3_l5 ! '/soc/pinctrl@f100000/qup0_se3_l6 ! 3/soc/pinctrl@f100000/qup0_se4_l0 ! ?/soc/pinctrl@f100000/qup0_se4_l1 ! K/soc/pinctrl@f100000/qup0_se4_l2 ! W/soc/pinctrl@f100000/qup0_se4_l3 ! c/soc/pinctrl@f100000/qup0_se5_l0 ! o/soc/pinctrl@f100000/qup0_se5_l1 ! {/soc/pinctrl@f100000/qup0_se5_l2 ! /soc/pinctrl@f100000/qup0_se5_l3 ! /soc/pinctrl@f100000/qup0_se6_l0 ! /soc/pinctrl@f100000/qup0_se6_l1 ! /soc/pinctrl@f100000/qup0_se6_l2 ! /soc/pinctrl@f100000/qup0_se6_l3 ! /soc/pinctrl@f100000/qup0_se7_l0 ! /soc/pinctrl@f100000/qup0_se7_l1 ! /soc/pinctrl@f100000/qup0_se7_l2 ! /soc/pinctrl@f100000/qup0_se7_l3 ! /soc/pinctrl@f100000/qup1_se0_l0 ! /soc/pinctrl@f100000/qup1_se0_l1 ! /soc/pinctrl@f100000/qup1_se0_l2 ! /soc/pinctrl@f100000/qup1_se0_l3 ! #/soc/pinctrl@f100000/qup1_se1_l0 ! //soc/pinctrl@f100000/qup1_se1_l1 ! ;/soc/pinctrl@f100000/qup1_se1_l2 ! G/soc/pinctrl@f100000/qup1_se1_l3 ! S/soc/pinctrl@f100000/qup1_se2_l0 ! _/soc/pinctrl@f100000/qup1_se2_l1 ! k/soc/pinctrl@f100000/qup1_se2_l2 ! w/soc/pinctrl@f100000/qup1_se2_l3 ! /soc/pinctrl@f100000/qup1_se2_l4 ! /soc/pinctrl@f100000/qup1_se2_l5 ! /soc/pinctrl@f100000/qup1_se2_l6 ! /soc/pinctrl@f100000/qup1_se3_l0 ! /soc/pinctrl@f100000/qup1_se3_l1 ! /soc/pinctrl@f100000/qup1_se3_l2 ! /soc/pinctrl@f100000/qup1_se3_l3 ! /soc/pinctrl@f100000/qup1_se3_l4 ! /soc/pinctrl@f100000/qup1_se3_l5 ! /soc/pinctrl@f100000/qup1_se3_l6 ! /soc/pinctrl@f100000/qup1_se4_l0 ! /soc/pinctrl@f100000/qup1_se4_l1 ! /soc/pinctrl@f100000/qup1_se4_l2 ! /soc/pinctrl@f100000/qup1_se4_l3 ! +/soc/pinctrl@f100000/qup1_se5_l0 ! 7/soc/pinctrl@f100000/qup1_se5_l1 ! C/soc/pinctrl@f100000/qup1_se5_l2 ! O/soc/pinctrl@f100000/qup1_se5_l3 ! [/soc/pinctrl@f100000/qup1_se6_l0 ! g/soc/pinctrl@f100000/qup1_se6_l1 ! s/soc/pinctrl@f100000/qup1_se6_l2 ! /soc/pinctrl@f100000/qup1_se6_l3 ! /soc/pinctrl@f100000/qup1_se7_l0 ! /soc/pinctrl@f100000/qup1_se7_l1 ! /soc/pinctrl@f100000/qup1_se7_l2 ! /soc/pinctrl@f100000/qup1_se7_l3 ! /soc/pinctrl@f100000/qup2_se0_l0 ! /soc/pinctrl@f100000/qup2_se0_l1 ! /soc/pinctrl@f100000/qup2_se0_l2 ! /soc/pinctrl@f100000/qup2_se0_l3 ! /soc/pinctrl@f100000/qup2_se1_l0 ! /soc/pinctrl@f100000/qup2_se1_l1 ! /soc/pinctrl@f100000/qup2_se1_l2 ! /soc/pinctrl@f100000/qup2_se1_l3 ! /soc/pinctrl@f100000/qup2_se2_l0 ! '/soc/pinctrl@f100000/qup2_se2_l1 ! 3/soc/pinctrl@f100000/qup2_se2_l2 ! ?/soc/pinctrl@f100000/qup2_se2_l3 ! K/soc/pinctrl@f100000/qup2_se2_l4 ! W/soc/pinctrl@f100000/qup2_se2_l5 ! c/soc/pinctrl@f100000/qup2_se2_l6 ! o/soc/pinctrl@f100000/qup2_se3_l0 ! {/soc/pinctrl@f100000/qup2_se3_l1 ! /soc/pinctrl@f100000/qup2_se3_l2 ! /soc/pinctrl@f100000/qup2_se3_l3 ! /soc/pinctrl@f100000/qup2_se3_l4 ! /soc/pinctrl@f100000/qup2_se3_l5 ! /soc/pinctrl@f100000/qup2_se3_l6 ! /soc/pinctrl@f100000/qup2_se4_l0 ! /soc/pinctrl@f100000/qup2_se4_l1 ! /soc/pinctrl@f100000/qup2_se4_l2 ! /soc/pinctrl@f100000/qup2_se4_l3 ! /soc/pinctrl@f100000/qup2_se5_l0 ! /soc/pinctrl@f100000/qup2_se5_l1 ! ! /soc/pinctrl@f100000/qup2_se5_l2 ! !/soc/pinctrl@f100000/qup2_se5_l3 ! !#/soc/pinctrl@f100000/qup2_se6_l0 ! !//soc/pinctrl@f100000/qup2_se6_l1 ! !;/soc/pinctrl@f100000/qup2_se6_l2 ! !G/soc/pinctrl@f100000/qup2_se6_l3 ! !S/soc/pinctrl@f100000/qup2_se7_l0 ! !_/soc/pinctrl@f100000/qup2_se7_l1 ! !k/soc/pinctrl@f100000/qup2_se7_l2 ! !w/soc/pinctrl@f100000/qup2_se7_l3 ! !/soc/pinctrl@f100000/qup3_se0_l0 ! !/soc/pinctrl@f100000/qup3_se0_l1 ! !/soc/pinctrl@f100000/qup3_se0_l2 ! !/soc/pinctrl@f100000/qup3_se0_l3 ! !/soc/pinctrl@f100000/qup3_se0_l4 ! !/soc/pinctrl@f100000/qup3_se0_l5 ! !/soc/pinctrl@f100000/qup3_se0_l6 ! !/soc/pinctrl@f100000/qup3_se0_l7 ! !/soc/pinctrl@f100000/qup3_se1_l0 ! !/soc/pinctrl@f100000/qup3_se1_l1 ! !/soc/pinctrl@f100000/qup3_se1_l2 ! "/soc/pinctrl@f100000/qup3_se1_l3 ! "/soc/pinctrl@f100000/qup3_se1_l4 ! " /soc/pinctrl@f100000/qup3_se1_l5 ! "+/soc/pinctrl@f100000/qup3_se1_l6 ! "7/soc/pinctrl@f100000/qup3_se1_l7 ( "C/soc/pinctrl@f100000/GPIO_config_active & "V/soc/pinctrl@f100000/GPIO_config_idle ' "g/soc/pinctrl@f100000/GPIO_config_sleep & "y/soc/pinctrl@f100000/GPIO_config_wake "/soc/pinctrl@7760000 ! "/soc/pinctrl@7760000/slimbus_clk " "/soc/pinctrl@7760000/slimbus_data . "/soc/pinctrl@7760000/slimbus_default_gpio_cfg "/soc/pinctrl@75C0000 % "/soc/pinctrl@75C0000/ssc_gpio_10_clk % "/soc/pinctrl@75C0000/ssc_gpio_11_clk % "/soc/pinctrl@75C0000/ssc_gpio_12_clk % "/soc/pinctrl@75C0000/ssc_gpio_13_clk % #/soc/pinctrl@75C0000/ssc_gpio_18_clk % # /soc/pinctrl@75C0000/ssc_gpio_19_clk % #./soc/pinctrl@75C0000/ssc_gpio_24_clk % #>/soc/pinctrl@75C0000/ssc_gpio_25_clk . #N/soc/pinctrl@75C0000/ssc_gpio_26_clk_reserved . #g/soc/pinctrl@75C0000/ssc_gpio_27_clk_reserved . #/soc/pinctrl@75C0000/ssc_gpio_28_clk_reserved . #/soc/pinctrl@75C0000/ssc_gpio_29_clk_reserved . #/soc/pinctrl@75C0000/ssc_gpio_30_clk_reserved . #/soc/pinctrl@75C0000/ssc_gpio_31_clk_reserved . #/soc/pinctrl@75C0000/ssc_gpio_34_clk_reserved . #/soc/pinctrl@75C0000/ssc_gpio_35_clk_reserved $ $/soc/pinctrl@75C0000/ssc_gpio_6_clk $ $%/soc/pinctrl@75C0000/ssc_gpio_7_clk % $4/soc/pinctrl@75C0000/ssc_qupv3_se0_0 % $D/soc/pinctrl@75C0000/ssc_qupv3_se0_1 & $T/soc/pinctrl@75C0000/ssc_qupv3_se10_0 & $e/soc/pinctrl@75C0000/ssc_qupv3_se10_1 & $v/soc/pinctrl@75C0000/ssc_qupv3_se10_2 & $/soc/pinctrl@75C0000/ssc_qupv3_se10_3 / $/soc/pinctrl@75C0000/ssc_qupv3_se11_0_reserved / $/soc/pinctrl@75C0000/ssc_qupv3_se11_1_reserved / $/soc/pinctrl@75C0000/ssc_qupv3_se11_2_reserved / $/soc/pinctrl@75C0000/ssc_qupv3_se11_3_reserved / % /soc/pinctrl@75C0000/ssc_qupv3_se12_0_reserved / %/soc/pinctrl@75C0000/ssc_qupv3_se12_1_reserved / %4/soc/pinctrl@75C0000/ssc_qupv3_se13_0_reserved / %N/soc/pinctrl@75C0000/ssc_qupv3_se13_1_reserved / %h/soc/pinctrl@75C0000/ssc_qupv3_se13_2_reserved / %/soc/pinctrl@75C0000/ssc_qupv3_se13_3_reserved / %/soc/pinctrl@75C0000/ssc_qupv3_se14_0_reserved / %/soc/pinctrl@75C0000/ssc_qupv3_se14_1_reserved % %/soc/pinctrl@75C0000/ssc_qupv3_se1_0 % %/soc/pinctrl@75C0000/ssc_qupv3_se1_1 . %/soc/pinctrl@75C0000/ssc_qupv3_se1_2_reserved . & /soc/pinctrl@75C0000/ssc_qupv3_se1_3_reserved % &"/soc/pinctrl@75C0000/ssc_qupv3_se2_0 % &2/soc/pinctrl@75C0000/ssc_qupv3_se2_1 % &B/soc/pinctrl@75C0000/ssc_qupv3_se2_2 % &R/soc/pinctrl@75C0000/ssc_qupv3_se2_3 % &b/soc/pinctrl@75C0000/ssc_qupv3_se2_4 % &r/soc/pinctrl@75C0000/ssc_qupv3_se2_5 % &/soc/pinctrl@75C0000/ssc_qupv3_se3_0 % &/soc/pinctrl@75C0000/ssc_qupv3_se3_1 % &/soc/pinctrl@75C0000/ssc_qupv3_se4_0 % &/soc/pinctrl@75C0000/ssc_qupv3_se4_1 % &/soc/pinctrl@75C0000/ssc_qupv3_se4_2 % &/soc/pinctrl@75C0000/ssc_qupv3_se4_3 % &/soc/pinctrl@75C0000/ssc_qupv3_se4_4 % &/soc/pinctrl@75C0000/ssc_qupv3_se4_5 % '/soc/pinctrl@75C0000/ssc_qupv3_se5_0 % '/soc/pinctrl@75C0000/ssc_qupv3_se5_1 % '"/soc/pinctrl@75C0000/ssc_qupv3_se5_2 % '2/soc/pinctrl@75C0000/ssc_qupv3_se5_3 % 'B/soc/pinctrl@75C0000/ssc_qupv3_se6_0 % 'R/soc/pinctrl@75C0000/ssc_qupv3_se6_1 % 'b/soc/pinctrl@75C0000/ssc_qupv3_se6_2 % 'r/soc/pinctrl@75C0000/ssc_qupv3_se6_3 % '/soc/pinctrl@75C0000/ssc_qupv3_se7_0 % '/soc/pinctrl@75C0000/ssc_qupv3_se7_1 % '/soc/pinctrl@75C0000/ssc_qupv3_se7_2 % '/soc/pinctrl@75C0000/ssc_qupv3_se7_3 % '/soc/pinctrl@75C0000/ssc_qupv3_se8_0 % '/soc/pinctrl@75C0000/ssc_qupv3_se8_1 . '/soc/pinctrl@75C0000/ssc_qupv3_se9_0_reserved . '/soc/pinctrl@75C0000/ssc_qupv3_se9_1_reserved - (/soc/pinctrl@75C0000/qup_ssc0_se0_i2c_active , (,/soc/pinctrl@75C0000/qup_ssc0_se0_i2c_sleep - (C/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_active , ([/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_sleep 1 (r/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_ibi_active 0 (/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_ibi_sleep - (/soc/pinctrl@75C0000/qup_ssc0_se1_i2c_active , (/soc/pinctrl@75C0000/qup_ssc0_se1_i2c_sleep - (/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_active , (/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_sleep 1 )/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_ibi_active 0 )#/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_ibi_sleep - )>/soc/pinctrl@75C0000/qup_ssc0_se2_i2c_active , )V/soc/pinctrl@75C0000/qup_ssc0_se2_i2c_sleep - )m/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_active , )/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_sleep 1 )/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_ibi_active 0 )/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_ibi_sleep - )/soc/pinctrl@75C0000/qup_ssc0_se2_spi_active , )/soc/pinctrl@75C0000/qup_ssc0_se2_spi_sleep . */soc/pinctrl@75C0000/qup_ssc0_se2_uart_active - */soc/pinctrl@75C0000/qup_ssc0_se2_uart_sleep - *3/soc/pinctrl@75C0000/qup_ssc0_se3_i2c_active , *K/soc/pinctrl@75C0000/qup_ssc0_se3_i2c_sleep - *b/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_active , *z/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_sleep 1 */soc/pinctrl@75C0000/qup_ssc0_se3_i3c_ibi_active 0 */soc/pinctrl@75C0000/qup_ssc0_se3_i3c_ibi_sleep - */soc/pinctrl@75C0000/qup_ssc0_se4_i2c_active , */soc/pinctrl@75C0000/qup_ssc0_se4_i2c_sleep - */soc/pinctrl@75C0000/qup_ssc0_se4_spi_active , +/soc/pinctrl@75C0000/qup_ssc0_se4_spi_sleep . +&/soc/pinctrl@75C0000/qup_ssc0_se4_uart_active - +?/soc/pinctrl@75C0000/qup_ssc0_se4_uart_sleep - +W/soc/pinctrl@75C0000/qup_ssc0_se5_i2c_active , +o/soc/pinctrl@75C0000/qup_ssc0_se5_i2c_sleep - +/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_active , +/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_sleep 1 +/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_ibi_active 0 +/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_ibi_sleep - +/soc/pinctrl@75C0000/qup_ssc0_se5_spi_active , ,/soc/pinctrl@75C0000/qup_ssc0_se5_spi_sleep . ,/soc/pinctrl@75C0000/qup_ssc0_se5_uart_active - ,4/soc/pinctrl@75C0000/qup_ssc0_se5_uart_sleep - ,L/soc/pinctrl@75C0000/qup_ssc0_se6_i2c_active , ,d/soc/pinctrl@75C0000/qup_ssc0_se6_i2c_sleep - ,{/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_active , ,/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_sleep 1 ,/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_ibi_active 0 ,/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_ibi_sleep - ,/soc/pinctrl@75C0000/qup_ssc0_se6_spi_active , ,/soc/pinctrl@75C0000/qup_ssc0_se6_spi_sleep . -/soc/pinctrl@75C0000/qup_ssc0_se6_uart_active - -)/soc/pinctrl@75C0000/qup_ssc0_se6_uart_sleep - -A/soc/pinctrl@75C0000/qup_ssc0_se7_i2c_active , -Y/soc/pinctrl@75C0000/qup_ssc0_se7_i2c_sleep - -p/soc/pinctrl@75C0000/qup_ssc0_se7_spi_active , -/soc/pinctrl@75C0000/qup_ssc0_se7_spi_sleep . -/soc/pinctrl@75C0000/qup_ssc0_se7_uart_active - -/soc/pinctrl@75C0000/qup_ssc0_se7_uart_sleep - -/soc/pinctrl@75C0000/qup_ssc0_se8_i2c_active , -/soc/pinctrl@75C0000/qup_ssc0_se8_i2c_sleep - -/soc/pinctrl@75C0000/qup_ssc0_se8_i3c_active , ./soc/pinctrl@75C0000/qup_ssc0_se8_i3c_sleep 1 ../soc/pinctrl@75C0000/qup_ssc0_se8_i3c_ibi_active 0 .J/soc/pinctrl@75C0000/qup_ssc0_se8_i3c_ibi_sleep . .e/soc/pinctrl@75C0000/qup_ssc0_se10_i2c_active - .~/soc/pinctrl@75C0000/qup_ssc0_se10_i2c_sleep . ./soc/pinctrl@75C0000/qup_ssc0_se10_spi_active - ./soc/pinctrl@75C0000/qup_ssc0_se10_spi_sleep / ./soc/pinctrl@75C0000/qup_ssc0_se10_uart_active . ./soc/pinctrl@75C0000/qup_ssc0_se10_uart_sleep
./soc/vdd_mxa
//soc/vdd_mxc /
/soc/vdd_cx //soc/vdd_lpi_mx / /soc/vdd_lpi_cx /'/soc/clock-controller@100000 /+/soc/clock-controller@1f40000 /8/soc/clock-controller@7700000 /H/soc/clock-controller@6bc0000 /W/soc/clock-controller@7b00000 /e/soc/clock-controller@6e40000 /t/soc/clock-controller@7a00000 /x/soc/cesta@7213000 //soc/funnel@10041000 //soc/funnel@11c44000 //soc/funnel@11c50000 //soc/funnel@11c04000 /soc/tnoc@11c31000 //soc/tnoc@11c39000 M/soc/tpda@11c47000 d/soc/tpda@11c53000 /soc/tpda@11c55000 0/soc/systemcache@20400000 0 /soc/spmi-bus@c400000 0(/soc/spmi-bus@c400000/pmic@0 6 02/soc/spmi-bus@c400000/pmic@0/spmi-vadc@92/therm_table 0>/soc/spmi-bus@c436000 0H/soc/spmi-bus@c447000 0R/soc/ibi_ssc_0_cfg@7500000 0`/soc/ibi_ssc_1_cfg@7510000 0n/soc/ibi_ssc_2_cfg@7520000 0|/soc/ibi_ssc_3_cfg@7530000 0/soc/ibi_ssc_4_cfg@7540000 0/soc/ibi_ssc_5_cfg@7550000 0/soc/ibi_ssc_6_cfg@7560000 9 0/soc/kernel_test_devices@0/interrupt-controller@10140000 0/sw model compatible #address-cells #size-cells proc-name chip-info phandle reg client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping offset out-mask timer-name timer-freq timer-num timer-interrupt ngpios width id qcom,strongpull egpio gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name mux config qcom,slewrate qcom,sleep-config regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id reg-names #clock-cells supported-hosts host remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name transport remote-ss ch-name options priority stack-size intents host-id fflags max-entries dest irq core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets base_port num_ports atid sync_period tpdm_name tpda tpda_port dataset cmb_size cti_channels cti_triggers dbg_regs pwrdbg_ctrl_reg lpi_funnel lpi_funnel_port port_lpass_lpi_dl_tpda port_lpass_lpi_crm_dl_tpda port_lpass_lpi_audio_hm_dl_tpda port_ddrss_lpi_slice0ddrss_lpi_trace_noc port_lpi_etm port_lpi_stm port_stm port_sdc_etm port_sdc_itm port_lpass_lpi_noc port_lpi_aon_noc port_aoc port_enpu0_noc port_enpu1_noc cti_name tnoc_id tnoc_funnel_name tpda_name port_occupied_mask tpda_funnel_name llcc-common-reg llcc-lcp-reg channel-mode-check lpi-base num-lpi-channels scid value use-interrupt sid mid pmic bid therm-tbl label hw-ch hw-settle avg-sp dec-ratio cal-method scaling scale-fcn pull-up asid arr_id table hw-common-params adctm-hw-params trip-range num_ssc_qup ibi_base protocol se_island_config tre_list_size ibi_se_index se_mode load_fw dfs_mode ibi_id gpii gpii_irq mgr_irq status clock-names clocks qup_id qup_common_offset se_wrapper_base_offset core_frequency qup_flags num_se sdc_gpii_list core_offset ibi_instance se_flags FIFO_MODE protocol_supported interface_supported num_gpiis ring_size_multiplier core_irq pdc_irq parent_wakeup_gpio shared_se od_frequency i2c_hs_i3c_src_freq is_pipeline_enable pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 num_top_qups irq_num qup0_cfg qup1_cfg qup2_cfg qup3_cfg gsi_pa tcsr_addr tcsr_gpii_offset tcsr_irq gpii_interrupts num_gpii active type uStructVer pszInstName uaMasterEA pszHwioBase uHwioBaseOffset uHwioBase hBamDev uIntId uBamIntId uMyEE smbus_clk smbus_data uGpioIntNum uaNumEndPoints uaVoltageVote bIsLpiTlmm LA uaEA uDataLineMask num_device_props tlmm_name_str svs_npa_str is_master default_clock_gear prog_bam_trust island_vote subsystem_sleep_vote tlmm_offset tlmm_val svs_npa use_gpio_int log_level no_retention num_local_ports local_port_base local_channel_base shared_channel_base num_local_counters is_lpm_used_for_mgr_bam_trans lpm_mgr_sb_region_base lpm_mgr_sb_region_size is_lpm_sat_sb_region_dump_enable lpm_sat_sb_region_base lpm_sat_sb_region_size ee_assign rev MmpmCoreIdType MmpmCoreInstanceIdType pClientName pwrCtrlFlag callBackFlag MMPM_Callback cbFcnStackSize interrupt-controller #interrupt-cells message service_id instance_id qdss_service_id image_idx eic_crash_enable eic_crash_type eic_crash_delay pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_binary_local_path pd_binary_remote_path pd_name pd_mon_install_attr pd_mon_image_sw_id subdomain_name pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable image_id pram_name pt_name wdog_irq_num err_irq_num code_ram_addr data_ram_addr code_ram_size data_ram_size pram_addr ssc_sdc_physpool_addr ssc_sdc_physpool_size ipcmem_physpool_addr ipcmem_physpool_size free-gpios interconnects interconnect-names interconnect-modes interconnect-0 interconnect-1 interconnect-2 llccs scid-mapping-reg clients dump-pools diag_cmd_request_f diag_start_stress_test_f diag_stress_test_loopback diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_flow_control_count_base diag_dsm_chained_count_base diag_get_cmd_reg_tbl diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_stress_test_delayed_rsp diag_drop_threshold_config diag_query_enable diag_get_time_api diag_get_drop_per diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_dsqb_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_drop_flow_cnt_incr diag_drop_per_step_max diag_drop_per_threshold_max diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks clientNum routes hw_instance masterIcbPort slaveIcbPort min index0 index1 index2 index3 index4 index5 index6 index7 index8 index9 index10 soc ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_legacy SystemTimer WakeUpTimer tlmm qup0_se0_l0 qup0_se0_l1 qup0_se0_l2 qup0_se0_l3 qup0_se1_l0 qup0_se1_l1 qup0_se1_l2 qup0_se1_l3 qup0_se2_l0 qup0_se2_l1 qup0_se2_l2 qup0_se2_l3 qup0_se2_l4 qup0_se2_l5 qup0_se2_l6 qup0_se3_l0 qup0_se3_l1 qup0_se3_l2 qup0_se3_l3 qup0_se3_l4 qup0_se3_l5 qup0_se3_l6 qup0_se4_l0 qup0_se4_l1 qup0_se4_l2 qup0_se4_l3 qup0_se5_l0 qup0_se5_l1 qup0_se5_l2 qup0_se5_l3 qup0_se6_l0 qup0_se6_l1 qup0_se6_l2 qup0_se6_l3 qup0_se7_l0 qup0_se7_l1 qup0_se7_l2 qup0_se7_l3 qup1_se0_l0 qup1_se0_l1 qup1_se0_l2 qup1_se0_l3 qup1_se1_l0 qup1_se1_l1 qup1_se1_l2 qup1_se1_l3 qup1_se2_l0 qup1_se2_l1 qup1_se2_l2 qup1_se2_l3 qup1_se2_l4 qup1_se2_l5 qup1_se2_l6 qup1_se3_l0 qup1_se3_l1 qup1_se3_l2 qup1_se3_l3 qup1_se3_l4 qup1_se3_l5 qup1_se3_l6 qup1_se4_l0 qup1_se4_l1 qup1_se4_l2 qup1_se4_l3 qup1_se5_l0 qup1_se5_l1 qup1_se5_l2 qup1_se5_l3 qup1_se6_l0 qup1_se6_l1 qup1_se6_l2 qup1_se6_l3 qup1_se7_l0 qup1_se7_l1 qup1_se7_l2 qup1_se7_l3 qup2_se0_l0 qup2_se0_l1 qup2_se0_l2 qup2_se0_l3 qup2_se1_l0 qup2_se1_l1 qup2_se1_l2 qup2_se1_l3 qup2_se2_l0 qup2_se2_l1 qup2_se2_l2 qup2_se2_l3 qup2_se2_l4 qup2_se2_l5 qup2_se2_l6 qup2_se3_l0 qup2_se3_l1 qup2_se3_l2 qup2_se3_l3 qup2_se3_l4 qup2_se3_l5 qup2_se3_l6 qup2_se4_l0 qup2_se4_l1 qup2_se4_l2 qup2_se4_l3 qup2_se5_l0 qup2_se5_l1 qup2_se5_l2 qup2_se5_l3 qup2_se6_l0 qup2_se6_l1 qup2_se6_l2 qup2_se6_l3 qup2_se7_l0 qup2_se7_l1 qup2_se7_l2 qup2_se7_l3 qup3_se0_l0 qup3_se0_l1 qup3_se0_l2 qup3_se0_l3 qup3_se0_l4 qup3_se0_l5 qup3_se0_l6 qup3_se0_l7 qup3_se1_l0 qup3_se1_l1 qup3_se1_l2 qup3_se1_l3 qup3_se1_l4 qup3_se1_l5 qup3_se1_l6 qup3_se1_l7 GPIO_config_active GPIO_config_idle GPIO_config_sleep GPIO_config_wake lpi_tlmm slimbus_clk slimbus_data slimbus_default_gpio_cfg ssc_tlmm ssc_gpio_10_clk ssc_gpio_11_clk ssc_gpio_12_clk ssc_gpio_13_clk ssc_gpio_18_clk ssc_gpio_19_clk ssc_gpio_24_clk ssc_gpio_25_clk ssc_gpio_26_clk_reserved ssc_gpio_27_clk_reserved ssc_gpio_28_clk_reserved ssc_gpio_29_clk_reserved ssc_gpio_30_clk_reserved ssc_gpio_31_clk_reserved ssc_gpio_34_clk_reserved ssc_gpio_35_clk_reserved ssc_gpio_6_clk ssc_gpio_7_clk ssc_qupv3_se0_0 ssc_qupv3_se0_1 ssc_qupv3_se10_0 ssc_qupv3_se10_1 ssc_qupv3_se10_2 ssc_qupv3_se10_3 ssc_qupv3_se11_0_reserved ssc_qupv3_se11_1_reserved ssc_qupv3_se11_2_reserved ssc_qupv3_se11_3_reserved ssc_qupv3_se12_0_reserved ssc_qupv3_se12_1_reserved ssc_qupv3_se13_0_reserved ssc_qupv3_se13_1_reserved ssc_qupv3_se13_2_reserved ssc_qupv3_se13_3_reserved ssc_qupv3_se14_0_reserved ssc_qupv3_se14_1_reserved ssc_qupv3_se1_0 ssc_qupv3_se1_1 ssc_qupv3_se1_2_reserved ssc_qupv3_se1_3_reserved ssc_qupv3_se2_0 ssc_qupv3_se2_1 ssc_qupv3_se2_2 ssc_qupv3_se2_3 ssc_qupv3_se2_4 ssc_qupv3_se2_5 ssc_qupv3_se3_0 ssc_qupv3_se3_1 ssc_qupv3_se4_0 ssc_qupv3_se4_1 ssc_qupv3_se4_2 ssc_qupv3_se4_3 ssc_qupv3_se4_4 ssc_qupv3_se4_5 ssc_qupv3_se5_0 ssc_qupv3_se5_1 ssc_qupv3_se5_2 ssc_qupv3_se5_3 ssc_qupv3_se6_0 ssc_qupv3_se6_1 ssc_qupv3_se6_2 ssc_qupv3_se6_3 ssc_qupv3_se7_0 ssc_qupv3_se7_1 ssc_qupv3_se7_2 ssc_qupv3_se7_3 ssc_qupv3_se8_0 ssc_qupv3_se8_1 ssc_qupv3_se9_0_reserved ssc_qupv3_se9_1_reserved qup_ssc0_se0_i2c_active qup_ssc0_se0_i2c_sleep qup_ssc0_se0_i3c_active qup_ssc0_se0_i3c_sleep qup_ssc0_se0_i3c_ibi_active qup_ssc0_se0_i3c_ibi_sleep qup_ssc0_se1_i2c_active qup_ssc0_se1_i2c_sleep qup_ssc0_se1_i3c_active qup_ssc0_se1_i3c_sleep qup_ssc0_se1_i3c_ibi_active qup_ssc0_se1_i3c_ibi_sleep qup_ssc0_se2_i2c_active qup_ssc0_se2_i2c_sleep qup_ssc0_se2_i3c_active qup_ssc0_se2_i3c_sleep qup_ssc0_se2_i3c_ibi_active qup_ssc0_se2_i3c_ibi_sleep qup_ssc0_se2_spi_active qup_ssc0_se2_spi_sleep qup_ssc0_se2_uart_active qup_ssc0_se2_uart_sleep qup_ssc0_se3_i2c_active qup_ssc0_se3_i2c_sleep qup_ssc0_se3_i3c_active qup_ssc0_se3_i3c_sleep qup_ssc0_se3_i3c_ibi_active qup_ssc0_se3_i3c_ibi_sleep qup_ssc0_se4_i2c_active qup_ssc0_se4_i2c_sleep qup_ssc0_se4_spi_active qup_ssc0_se4_spi_sleep qup_ssc0_se4_uart_active qup_ssc0_se4_uart_sleep qup_ssc0_se5_i2c_active qup_ssc0_se5_i2c_sleep qup_ssc0_se5_i3c_active qup_ssc0_se5_i3c_sleep qup_ssc0_se5_i3c_ibi_active qup_ssc0_se5_i3c_ibi_sleep qup_ssc0_se5_spi_active qup_ssc0_se5_spi_sleep qup_ssc0_se5_uart_active qup_ssc0_se5_uart_sleep qup_ssc0_se6_i2c_active qup_ssc0_se6_i2c_sleep qup_ssc0_se6_i3c_active qup_ssc0_se6_i3c_sleep qup_ssc0_se6_i3c_ibi_active qup_ssc0_se6_i3c_ibi_sleep qup_ssc0_se6_spi_active qup_ssc0_se6_spi_sleep qup_ssc0_se6_uart_active qup_ssc0_se6_uart_sleep qup_ssc0_se7_i2c_active qup_ssc0_se7_i2c_sleep qup_ssc0_se7_spi_active qup_ssc0_se7_spi_sleep qup_ssc0_se7_uart_active qup_ssc0_se7_uart_sleep qup_ssc0_se8_i2c_active qup_ssc0_se8_i2c_sleep qup_ssc0_se8_i3c_active qup_ssc0_se8_i3c_sleep qup_ssc0_se8_i3c_ibi_active qup_ssc0_se8_i3c_ibi_sleep qup_ssc0_se10_i2c_active qup_ssc0_se10_i2c_sleep qup_ssc0_se10_spi_active qup_ssc0_se10_spi_sleep qup_ssc0_se10_uart_active qup_ssc0_se10_uart_sleep vdd_mxa vdd_mxc vdd_cx vdd_lpi_mx vdd_lpi_cx gcc lpass_aon_cc lpass_aon_mx_cc lpass_audio_cc lpass_core_cc lpass_lpmla_cc scc lpass_cesta in_fun0_in_fun0_cxatbfunnel lpass_lpi_fun0_fun0_cxatbfunnel lpass_lpi_fun1_fun1_cxatbfunnel aoss_apb_fun0 ddrss_lpi_slice1ddrss_lpi_trace_noc systemcache0 spmi_bus pmk8850_0 therm_table spmi_bus1 spmi_bus2 ibi_ssc_0_cfg ibi_ssc_1_cfg ibi_ssc_2_cfg ibi_ssc_3_cfg ibi_ssc_4_cfg ibi_ssc_5_cfg ibi_ssc_6_cfg intc sw
X 8
x (
@ qcom,glymur qcom,glymur board-id ,audio_process-glymur-1.0-adsp 6 soc @ cxstmtrace@16000000 qcom,stmtrace H L V @ lpistmtrace@7100000 qcom,stmtrace H L V @ sw @ core cpt_boot_test ` ` l w test1 l w * My Secret Message, Please keep it secret! test2 test_types U
U#4 4VxeC! % ( <穣4VxܺvT2 M test_pic_3 qcom,pic d test_uart1
qcom,uart d lbase rx tx test_uart2
qcom,uart d PD_Access_control v U OEM_Flavor_Validation mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config ! debugtrace qcom,debugtrace debugtools tms_diag qcom,tms_diag eic qcom,eic Z version_tbl qcom,image_version_tbl_idx power qdsp_pm pd qcom,pd-audio-process diag qcom,audio_user_diagcfg diagcfg_cmd g i 3 = Q l diagcfg_param : N c 2 1 G ` z AUDIO_ISLAND_TCM_PHYSPOOL QSH_ISLAND_POOL __symbols__ /soc /sw model compatible #address-cells #size-cells proc-name chip-info phandle reg base_port num_ports test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint16 test_uint32 test_uint32_list test_uint64 test_string test_uint8 test_uint8_list_empty test_uint16_list test_uint16_list_empty test_uint32_list_empty test_uint64_list test_uint64_list_empty reg_alt reg-names PD_indicator test_oem_entry service_id instance_id qdss_service_id image_id eic_crash_enable eic_crash_type eic_crash_delay image_idx QDI_QDSP_PM_USER_ID diag_test_cmd_f diag_v2_test_cmd_f diag_legacy_health_count_base diag_ulogdiag_processor_id diag_subsys_id_base diag_lsm_cmd_reg_test_base diag_get_set_drain_param diag_f3_trace_set_config diag_health_stats_base diag_err_ulog_size diag_debug_ulog_size diag_qdss_ulog_size diag_logtracker_ulog_size diag_dsqb_ulog_size diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_event_send_max diag_multipd_buf_size diag_multipd_event_heap_size diag_send_buf_size_data_userpd diag_lsm_stack_size diag_stress_task_sleep_complete diag_deferrable_timer diag_deferrable_timer_ex diag_msg_fmt_str_arg_size diag_uimage_mpd_buf_size diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool soc sw
h 8 ( qcom,glymur qcom,glymur board-id ,qsh_process-glymur-1.0-adsp 6 soc @ cxstmtrace@16000000 qcom,stmtrace H L @ V @ lpistmtrace@7100000 qcom,stmtrace H L @ V @ sw @ core cpt_boot_test PD_Access_control ` X OEM_Flavor_Validation m mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config | " debugtrace qcom,debugtrace debugtools tms_diag qcom,tms_diag eic qcom,eic Z version_tbl qcom,image_version_tbl_idx power qdsp_pm pd qcom,pd-qsh-process products sdcloader qcom,sdcloader sdc_params < ! / = Ka sdc_physpool U k 'P diag qcom,sensor_user_diagcfg diagcfg_cmd h j = 6 O h' diagcfg_param 2 2 F \ y . LQSH_ISLAND_POOL ]QSH_ISLAND_POOL qup_user_pd_feature qcom,sw-qup-user-pd-controller s __symbols__ /soc /sw model compatible #address-cells #size-cells proc-name chip-info phandle reg base_port num_ports PD_indicator test_oem_entry service_id instance_id qdss_service_id image_id eic_crash_enable eic_crash_type eic_crash_delay image_idx QDI_QDSP_PM_USER_ID wdog_irq_num err_irq_num code_ram_addr data_ram_addr code_ram_size data_ram_size pram_addr ssc_sdc_physpool_addr ssc_sdc_physpool_size ipcmem_physpool_addr ipcmem_physpool_size diag_test_cmd_f diag_v2_test_cmd_f diag_legacy_health_count_base diag_ulogdiag_processor_id diag_subsys_id_base diag_lsm_cmd_reg_test_base diag_get_set_drain_param diag_f3_trace_set_config diag_health_stats_base diag_err_ulog_size diag_debug_ulog_size diag_qdss_ulog_size diag_logtracker_ulog_size diag_dsqb_ulog_size diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_event_send_max diag_multipd_buf_size diag_multipd_event_heap_size diag_send_buf_size_data_userpd diag_lsm_stack_size diag_stress_task_sleep_complete diag_deferrable_timer diag_deferrable_timer_ex diag_msg_fmt_str_arg_size diag_uimage_mpd_buf_size diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool user_pd_island_enabled soc sw
` 8 ]` ( / ]( qcom,mahua qcom,mahua board-id ,default_process-mahua-1.0-adsp 6 soc @ z ipcc
qcom,ipcc ipcc@3e02000 qcom,ipcc-protocol H L SMPROC a n y D ! " : ; < - . 7 8 @ { ipcc@3e40000 qcom,ipcc-protocol H L SCOMPUTE_L0 a n N 0 ! "
- . @ | ipcc@3e80000 qcom,ipcc-protocol H L SCOMPUTE_L1 a n 0 ! "
- . @ } ipcc@3ec0000 qcom,ipcc-protocol H L SPERIPH a n D
! " , - . 7 8 @ ~ ipcc_legacy@6888004 H @ ipcc_legacy_sdc qcom,ipcc-legacy L n 8 9 : ; @ timetick timer@68a2000 qcom,timetick H SystemTimer $ @ timer@68a3000 qcom,timetick H0 WakeUpTimer $ @ pinctrl@f100000 ! qcom,glymur-pinctrl qcom,pinctrl H n > O V B u $ } P 4summary directconn0 directconn1 directconn2 directconn3 directconn4 directconn5 D WGPIOINTADSP @ qup0_se0_l0 h @ qup0_se0_l1 h @ qup0_se0_l2 h @ qup0_se0_l3 h @ qup0_se1_l0 h @ qup0_se1_l1 h @ qup0_se1_l2 h @ qup0_se1_l3 h @ qup0_se2_l0 h @ qup0_se2_l1 h @ qup0_se2_l2 h
@ qup0_se2_l3 h @ qup0_se2_l4 h @ qup0_se2_l5 h @ qup0_se2_l6 h @ qup0_se3_l0 h @ qup0_se3_l1 h
@ qup0_se3_l2 h @ qup0_se3_l3 h @ qup0_se3_l4 h @ qup0_se3_l5 h @ qup0_se3_l6 h @ qup0_se4_l0 h @ qup0_se4_l1 h @ qup0_se4_l2 h @ qup0_se4_l3 h @ qup0_se5_l0 h @ qup0_se5_l1 h @ qup0_se5_l2 h @ qup0_se5_l3 h @ qup0_se6_l0 h @ qup0_se6_l1 h @ qup0_se6_l2 h @ qup0_se6_l3 h @ qup0_se7_l0 h @ qup0_se7_l1 h @ qup0_se7_l2 h @ qup0_se7_l3 h
@ qup1_se0_l0 h @ qup1_se0_l1 h ! @ qup1_se0_l2 h " @ qup1_se0_l3 h # @ qup1_se1_l0 h $ @ qup1_se1_l1 h % @ qup1_se1_l2 h & @ qup1_se1_l3 h ' @ qup1_se2_l0 h ( @ qup1_se2_l1 h ) @ qup1_se2_l2 h * @ qup1_se2_l3 h + @ qup1_se2_l4 h 1 @ qup1_se2_l5 h 2 @ qup1_se2_l6 h 3 @ qup1_se3_l0 h , @ qup1_se3_l1 h - @ qup1_se3_l2 h . @ qup1_se3_l3 h / @ qup1_se3_l4 h ! @ qup1_se3_l5 h " @ qup1_se3_l6 h # @ qup1_se4_l0 h 0 @ qup1_se4_l1 h 1 @ qup1_se4_l2 h 2 @ qup1_se4_l3 h 3 @ qup1_se5_l0 h 4 @ qup1_se5_l1 h 5 @ qup1_se5_l2 h 6 @ qup1_se5_l3 h 7 @ qup1_se6_l0 h 8 @ qup1_se6_l1 h 9 @ qup1_se6_l2 h : @ qup1_se6_l3 h ; @ qup1_se7_l0 h 6 @ qup1_se7_l1 h 7 @ qup1_se7_l2 h 4 @ qup1_se7_l3 h 5 @ qup2_se0_l0 h @ @ qup2_se0_l1 h A @ qup2_se0_l2 h B @ qup2_se0_l3 h C @ qup2_se1_l0 h D @ qup2_se1_l1 h E @ qup2_se1_l2 h F @ qup2_se1_l3 h G @ qup2_se2_l0 h H @ qup2_se2_l1 h I @ qup2_se2_l2 h J @ qup2_se2_l3 h K @ qup2_se2_l4 h Q @ qup2_se2_l5 h R @ qup2_se2_l6 h S @ qup2_se3_l0 h L @ qup2_se3_l1 h M @ qup2_se3_l2 h N @ qup2_se3_l3 h O @ qup2_se3_l4 h A @ qup2_se3_l5 h B @ qup2_se3_l6 h C @ qup2_se4_l0 h P @ qup2_se4_l1 h Q @ qup2_se4_l2 h R @ qup2_se4_l3 h S @ qup2_se5_l0 h T @ qup2_se5_l1 h U @ qup2_se5_l2 h V @ qup2_se5_l3 h W @ qup2_se6_l0 h X @ qup2_se6_l1 h Y @ qup2_se6_l2 h Z @ qup2_se6_l3 h [ @ qup2_se7_l0 h P @ qup2_se7_l1 h Q @ qup2_se7_l2 h R @ qup2_se7_l3 h S @ qup3_se0_l0 h @ qup3_se0_l1 h @ qup3_se0_l2 h @ qup3_se0_l3 h @ qup3_se0_l4 h @ qup3_se0_l5 h @ qup3_se0_l6 h @ qup3_se0_l7 h @ qup3_se1_l0 h ( @ qup3_se1_l1 h ) @ qup3_se1_l2 h * @ qup3_se1_l3 h + @ qup3_se1_l4 h 1 @ qup3_se1_l5 h 2 @ qup3_se1_l6 h 3 @ qup3_se1_l7 h 0 @ pinctrl@7760000 ! qcom,glymur-pinctrl qcom,pinctrl Hv l l z E E E E E E E E E E E E E E E E E E E E E E E E E E E @ slimbus_clk h @ slimbus_data h @ slimbus_default_gpio_cfg ! ! @ x pinctrl@75C0000 ! qcom,glymur-pinctrl qcom,pinctrl H\ - z a a E E Q Q E E a a E E E E I E Q Q E E E E E E E E E E E E E E E E E E E E Q Q E E E E E @ ssc_gpio_10_clk h
@ ssc_gpio_11_clk h @ ssc_gpio_12_clk h @ ssc_gpio_13_clk h
@
ssc_gpio_18_clk h @ ssc_gpio_19_clk h @ ssc_gpio_24_clk h @
ssc_gpio_25_clk h @ ssc_gpio_26_clk_reserved h @ ssc_gpio_27_clk_reserved h @ ssc_gpio_28_clk_reserved h @ ssc_gpio_29_clk_reserved h @ ssc_gpio_30_clk_reserved h @ ssc_gpio_31_clk_reserved h @ ssc_gpio_34_clk_reserved h " @ ssc_gpio_35_clk_reserved h # @ ssc_gpio_6_clk h @ ssc_gpio_7_clk h @ ssc_qupv3_se0_0 h @ ssc_qupv3_se0_1 h @ ssc_qupv3_se10_0 h @ ssc_qupv3_se10_1 h @ ! ssc_qupv3_se10_2 h @ " ssc_qupv3_se10_3 h @ # ssc_qupv3_se11_0_reserved h @ ssc_qupv3_se11_1_reserved h @ ssc_qupv3_se11_2_reserved h @ ssc_qupv3_se11_3_reserved h @ ssc_qupv3_se12_0_reserved h @ ssc_qupv3_se12_1_reserved h @ ssc_qupv3_se13_0_reserved h @ ssc_qupv3_se13_1_reserved h ! @ ssc_qupv3_se13_2_reserved h " @ ! ssc_qupv3_se13_3_reserved h # @ " ssc_qupv3_se14_0_reserved h $ @ # ssc_qupv3_se14_1_reserved h % @ $ ssc_qupv3_se1_0 h @ ssc_qupv3_se1_1 h @ ssc_qupv3_se1_2_reserved h @ % ssc_qupv3_se1_3_reserved h @ & ssc_qupv3_se2_0 h @ ssc_qupv3_se2_1 h @ ssc_qupv3_se2_2 h @
ssc_qupv3_se2_3 h @ ssc_qupv3_se2_4 h @ ' ssc_qupv3_se2_5 h @ ( ssc_qupv3_se3_0 h @ ssc_qupv3_se3_1 h @
ssc_qupv3_se4_0 h
@ ssc_qupv3_se4_1 h @ ssc_qupv3_se4_2 h @ ssc_qupv3_se4_3 h
@ ssc_qupv3_se4_4 h @ ) ssc_qupv3_se4_5 h @ * ssc_qupv3_se5_0 h @ ssc_qupv3_se5_1 h @ ssc_qupv3_se5_2 h @ ssc_qupv3_se5_3 h @ ssc_qupv3_se6_0 h @ ssc_qupv3_se6_1 h @ ssc_qupv3_se6_2 h @ ssc_qupv3_se6_3 h @ ssc_qupv3_se7_0 h @ ssc_qupv3_se7_1 h @ ssc_qupv3_se7_2 h @ ssc_qupv3_se7_3 h @ ssc_qupv3_se8_0 h @ ssc_qupv3_se8_1 h @ ssc_qupv3_se9_0_reserved h @ + ssc_qupv3_se9_1_reserved h @ , qup_ssc0_se0_i2c_active @ 0 qup_ssc0_se0_i2c_sleep @ 1 qup_ssc0_se0_i3c_active
@ 2 qup_ssc0_se0_i3c_sleep ! ! @ 3 qup_ssc0_se0_i3c_ibi_active
@ 4 qup_ssc0_se0_i3c_ibi_sleep ! ! @ 5 qup_ssc0_se1_i2c_active @ 6 qup_ssc0_se1_i2c_sleep @ 7 qup_ssc0_se1_i3c_active
@ 8 qup_ssc0_se1_i3c_sleep ! ! @ 9 qup_ssc0_se1_i3c_ibi_active
@ : qup_ssc0_se1_i3c_ibi_sleep ! ! @ ; qup_ssc0_se2_i2c_active @ < qup_ssc0_se2_i2c_sleep @ = qup_ssc0_se2_i3c_active
@ > qup_ssc0_se2_i3c_sleep ! ! @ ? qup_ssc0_se2_i3c_ibi_active
@ @ qup_ssc0_se2_i3c_ibi_sleep ! ! @ A qup_ssc0_se2_spi_active X X
X X @ B qup_ssc0_se2_spi_sleep ! !
! ! @ C qup_ssc0_se2_uart_active
@ D qup_ssc0_se2_uart_sleep
@ E qup_ssc0_se3_i2c_active
@ F qup_ssc0_se3_i2c_sleep
@ G qup_ssc0_se3_i3c_active
@ H qup_ssc0_se3_i3c_sleep !
! @ I qup_ssc0_se3_i3c_ibi_active
@ J qup_ssc0_se3_i3c_ibi_sleep !
! @ K qup_ssc0_se4_i2c_active @ L qup_ssc0_se4_i2c_sleep @ M qup_ssc0_se4_spi_active X X X X @ N qup_ssc0_se4_spi_sleep ! ! ! ! @ O qup_ssc0_se4_uart_active @ P qup_ssc0_se4_uart_sleep @ Q qup_ssc0_se5_i2c_active @ R qup_ssc0_se5_i2c_sleep @ S qup_ssc0_se5_i3c_active
@ T qup_ssc0_se5_i3c_sleep ! ! @ U qup_ssc0_se5_i3c_ibi_active
@ V qup_ssc0_se5_i3c_ibi_sleep ! ! @ W qup_ssc0_se5_spi_active X X X X @ X qup_ssc0_se5_spi_sleep ! ! ! ! @ Y qup_ssc0_se5_uart_active @ Z qup_ssc0_se5_uart_sleep @ [ qup_ssc0_se6_i2c_active @ \ qup_ssc0_se6_i2c_sleep @ ] qup_ssc0_se6_i3c_active
@ ^ qup_ssc0_se6_i3c_sleep ! ! @ _ qup_ssc0_se6_i3c_ibi_active
@ ` qup_ssc0_se6_i3c_ibi_sleep ! ! @ a qup_ssc0_se6_spi_active X X X X @ b qup_ssc0_se6_spi_sleep ! ! ! ! @ c qup_ssc0_se6_uart_active @ d qup_ssc0_se6_uart_sleep @ e qup_ssc0_se7_i2c_active @ f qup_ssc0_se7_i2c_sleep @ g qup_ssc0_se7_spi_active X X X X @ h qup_ssc0_se7_spi_sleep ! ! ! ! @ i qup_ssc0_se7_uart_active @ j qup_ssc0_se7_uart_sleep @ k qup_ssc0_se8_i2c_active @ l qup_ssc0_se8_i2c_sleep @ m qup_ssc0_se8_i3c_active
@ n qup_ssc0_se8_i3c_sleep ! ! @ o qup_ssc0_se8_i3c_ibi_active
@ p qup_ssc0_se8_i3c_ibi_sleep ! ! @ q qup_ssc0_se10_i2c_active ! @ r qup_ssc0_se10_i2c_sleep ! @ s qup_ssc0_se10_spi_active X !X "X #X @ t qup_ssc0_se10_spi_sleep ! ! ! " ! # ! @ u qup_ssc0_se10_uart_active ! " # @ v qup_ssc0_se10_uart_sleep ! " # @ w vdd_mxa qcom,rpmh-arc-regulator /vcs/vdd_mxa /vcs/vdd_mx mx.lvl
@ - vdd_mxc qcom,rpmh-arc-regulator
/vcs/vdd_mxc mxc.lvl
@ . vdd_cx qcom,rpmh-arc-regulator /vcs/vdd_cx cx.lvl
@ / vdd_lpi_mx qcom,rpmh-arc-regulator /vcs/vdd_lpi_mx /vcs/vdd_ssc_mx lmx.lvl
? @ 0 vdd_lpi_cx qcom,rpmh-arc-regulator ! /vcs/vdd_lpi_cx /vcs/vdd_ssc_int lcx.lvl
? @ 1 clock-controller@100000 qcom,gcc-glymur qcom,cc-glymur H 0 @ P ` p 0 @ / / )GCC_GPLL0_CM_PLL_TAYCAN_COMMON GCC_GPLL1_CM_PLL_TAYCAN_COMMON GCC_GPLL2_CM_PLL_TAYCAN_COMMON GCC_GPLL3_CM_PLL_TAYCAN_COMMON GCC_GPLL4_CM_PLL_TAYCAN_COMMON GCC_GPLL5_CM_PLL_TAYCAN_COMMON GCC_GPLL6_CM_PLL_TAYCAN_COMMON GCC_GPLL7_CM_PLL_TAYCAN_COMMON GCC_GPLL8_CM_PLL_TAYCAN_COMMON GCC_GPLL9_CM_PLL_TAYCAN_COMMON GCC_GPLL10_CM_PLL_ZONDA_COMMON GCC_GPLL11_CM_PLL_ZONDA_COMMON GCC_GPLL12_CM_PLL_ZONDA_COMMON GCC_GPLL13_CM_PLL_ZONDA_COMMON GCC_GPLL14_CM_PLL_TAYCAN_COMMON GCC_GPLL15_CM_PLL_TAYCAN_COMMON GCC_GPLL16_CM_PLL_TAYCAN_COMMON GCC_GPLL17_CM_PLL_TAYCAN_COMMON GCC_GPLL18_CM_PLL_TAYCAN_COMMON GCC_GPLL19_CM_PLL_TAYCAN_COMMON GCC_JBIST_CM_PLL_JBIST4_COMMON GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_RPUQ11_512_CL36L12_LE GCC_RPU_XPU4 3 @ 2 clock-controller@1f40000 ( qcom,lpass_aon_cc-glymur qcom,cc-glymur P H ` p & < )TCSR_TCSR_REGS LPASS_QDSP6SS_QDSP6SS_PUB LPASS_QDSP6SS_QDSP6SS_QDSP6SSV81_CORE_CC_SWI LPASS_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON LPASS_QDSP6SS_QDSP6SSV81_CORE_CC_REG LPASS_AON_CC_PLL_CM_PLL_TAYCAN_COMMON LPASS_AON_CC_AHB2PHY_SWMAN LPASS_AON_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_CC_LPASS_AON_CC_REG LPASS_LPI_TCM_REG 3 @ . clock-controller@7700000 + qcom,lpass_aon_mx_cc-glymur qcom,cc-glymur Hp p` pp p )LPASS_AON_MX_CC_RO_PLL_CM_PLL_PONGO_COMMON LPASS_AON_MX_CC_AHB2PHY_SWMAN LPASS_AON_MX_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_MX_CC_LPASS_AON_MX_CC_REG 3 @ 3 clock-controller@6bc0000 * qcom,lpass_audio_cc-glymur qcom,cc-glymur 0 H ` p )LPASS_AUDIO_CC_PLL_CM_PLL_ZONDA_COMMON LPASS_AUDIO_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_AUDIO_CC_LCC_PLL_CM_PLL_JBIST4_COMMON LPASS_AUDIO_CC_AHB2PHY_SWMAN LPASS_AUDIO_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AUDIO_CC_LPASS_AUDIO_CC_REG 3 @ 4 clock-controller@7b00000 ) qcom,lpass_core_cc-glymur qcom,cc-glymur 0 H ` p 0 )LPASS_LPASS_CORE_CC_DIG_PLL_LPASS_CORE_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_LPASS_CORE_CC_REG LPASS_HW_AF_CORE LPASS_CORE_GDSC 3 @ 5 clock-controller@6e40000 * qcom,lpass_lpmla_cc-glymur qcom,cc-glymur H ` p @ )LPASS_LPMLA_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPMLA_CC_AHB2PHY_SWMAN LPASS_LPMLA_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPMLA_CC_LPASS_LPMLA_CC_REG 3 @ 6 clock-controller@7a00000 qcom,scc-glymur qcom,cc-glymur H )SSC_SCC_SCC_SCC_REG 3 @ / cesta@7213000 ' qcom,lpass_cesta-glymur qcom,cc-glymur ( H!0 !4 !8 !X !_ @ )LPASS_CRMB LPASS_CRMB_PT LPASS_CRMC LPASS_CRMV LPASS_CRM_COMMON @ 7 glink qcom,glink @ proc-info P xport-smem-config edge-01 U a @ k t | N xport-qmp-config edge-01 aop_adsp U t @ ipc_router qcom,ipc_router proc-info adsp devcfg-glink-xals edge-01 SMEM apss IPCRTR ( 1 < smp2p qcom,smp2p proc-info D L S smp2p-interrupts intr-01 _ R d intr-02 _ R d smem
qcom,smem
hCORE_TOP_CSR y 0
@
@ cxstmtrace@16000000 qcom,stmtrace H lpistmtrace@7100000 qcom,stmtrace H @ cxstmcfg@10002000 qcom,stmcfg H lpistmcfg@11c43000 qcom,stmcfg H0 cxetb@11c05000 qcom,tmc HP lpietb@11c45000 qcom,tmc HP tpdm@11c46000
qcom,tpdm H` tpdm_31 $ tpdm@11c52000
qcom,tpdm H tpdm_62 % tpdm@11c54000
qcom,tpdm H@ tpdm_22 & tpdm@11c34000
qcom,tpdm H@ tpdm_50 ' tpdm@11c3c000
qcom,tpdm H tpdm_8 ( qdss 0
L L !_!_ & ) 1 A * + ) X * + ) s * + ) ) + ) + * + ) , ) + ) + ) + ) + ) + ) & * + ) 5 * + ) cti@11c35000 qcom,cti ( Dddrss_lpi_slice0cti_cti_qc_cti_extended HP cti@11c42000 qcom,cti $ Dlpass_lpi_cti_sdc_2_cti_sdc_2_cscti H cti@11c4b000 qcom,cti & Dlpass_lpi_qdsp6_qdsp6ss_qdsp6ss_cscti Hİ cti@11c51000 qcom,cti " Dlpass_lpi_cti_3_cti_3_qc_cti_core H cti@11c41000 qcom,cti " Dlpass_lpi_cti_1_cti_1_qc_cti_core H cti@11c3d000 qcom,cti ( Dddrss_lpi_slice1cti_cti_qc_cti_extended H qdss_lpi_csr@6ee0000 qcom,qdss_lpi_csr H funnel@10041000
qcom,tfunnel H @ , funnel@11c44000
qcom,tfunnel H@ @ + funnel@11c50000
qcom,tfunnel H @ * funnel@11c04000
qcom,tfunnel H@ @ ) tnoc@11c31000
qcom,tnoc M ' H * ) Uport_ddrss_lpi_slice0ddrss_lpi_trace_noc @ ' tnoc@11c39000
qcom,tnoc M ( HÐ 9 ) Uport_ddrss_lpi_slice0ddrss_lpi_trace_noc @ ( tpda@11c47000
qcom,tpda Hp ftpda_26 p port_lpass_lpi_dl_tpda @ $ tpda@11c53000
qcom,tpda H0 ftpda_55 7 p port_lpass_lpi_crm_dl_tpda @ % tpda@11c55000
qcom,tpda HP ftpda_56 8 p port_lpass_lpi_audio_hm_dl_tpda @ & systemcache@20400000 qcom,systemcache X H @ ` ! ! ! ! " " " " ( )llcc_bcast_or_base llcc_bcast_and_base llcc0_base llcc1_base llcc2_base llcc3_base llcc4_base llcc5_base llcc6_base llcc7_base ddrss_regs_base @ @ y llc-island qcom,llc-island islands р island@c,80000000 H X subsys_instance qcom,subsys_instance spmi-bus@c400000 qcom,spmi-pmic-arb H @ @ 8 pmic@0 qcom,spmi-pmic H @ 9 spmi-vadc@92 qcom,spmi-vadc H - vadc_ch_cfg VPH_PWR VPH_PWR $ + 5 @ H R Z vadc-avg-ch gpio-map therm_table @ - therm_tb1 _ f @x - $ R Ȩ (l m % 1 z % * 5` / 4 9 > C i H V M G| R ;` W 18 \ )h a " f L k p " u z
\
vadctm_meas_cfg l VPH_PWR VPH_PWR } @ H Z ' spmi-bus@c436000 qcom,spmi-pmic-arb H @ @ : spmi-bus@c447000 qcom,spmi-pmic-arb H @ @ ; ssc_qup_fw_cfg qcom,qupfw-controller ssc_qup_0 se0_cfg P se1_cfg @ Q se2_cfg R se3_cfg S se4_cfg se5_cfg @ T se6_cfg U se7_cfg se8_cfg
V se10_cfg
ibi_ssc_0_cfg@7500000 qcom,ibi-controller HP M G ! ok @ < ibi_ssc_1_cfg@7510000 qcom,ibi-controller HQ M f ok @ = ibi_ssc_2_cfg@7520000 qcom,ibi-controller HR M ok @ > ibi_ssc_3_cfg@7530000 qcom,ibi-controller HS M ok @ ? ibi_ssc_4_cfg@7540000 qcom,ibi-controller HT M ok @ @ ibi_ssc_5_cfg@7550000 qcom,ibi-controller HU M ok @ A ibi_ssc_6_cfg@7560000 qcom,ibi-controller HV M ok @ B ssc_pwr_domains qcom,ssc-pwr-domain-controller ssc_gdsc + .@H SSC_QUP_0@7900000 qcom,sscqup-controller H core2x core s-ahb m-ahb + /Sd /d4 /v /^, 2 9 K bр q {
ok SSC_QUP_0_SE_0 qcom,se-controller + & 0 = Q se-clk + /H J di2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep r 0 | 1 2 3 4 5 ok SSC_QUP_0_SE_1 qcom,se-controller @ , p & 0 = Q se-clk + / Ǟ J di2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep r 6 | 7 8 9 : ; ok SSC_QUP_0_SE_2 qcom,se-controller - & 0 = Q se-clk + /~E: x di2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep r < | = > ? @ A B C D E ok SSC_QUP_0_SE_3 qcom,se-controller . & 0 = Q se-clk + / w J di2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep r F | G H I J K ok SSC_QUP_0_SE_4 qcom,se-controller / & 0 = Q se-clk + /*̉ D di2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep r L | M N O P Q ok SSC_QUP_0_SE_5 qcom,se-controller @ 0 w & 0 = Q se-clk + / x di2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep r R | S T U V W X Y Z [ ok SSC_QUP_0_SE_6 qcom,se-controller 1 & 0 = Q se-clk + / x di2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep r \ | ] ^ _ ` a b c d e ok SSC_QUP_0_SE_7 qcom,se-controller * & 0 = Q se-clk + /O D di2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep r f | g h i j k ok SSC_QUP_0_SE_8 qcom,se-controller ) & 0 = Q se-clk + /pP J di2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep r l | m n o p q ok SSC_QUP_0_SE_10 qcom,se-controller
& 0 = Q se-clk + / D di2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep r r | s t u v w ok qup_tcsr_info qcom,quptcsr-controller tcsr_cfg0 k
tcsr_cfg1
gsi_info qcom,gsi-controller gsi_qup_0 @ T 1 Z @ : J S Z gsi_qup_1 @ h 1 [ @ : J S Z gsi_qup_2 @ 1 d @ : J S Z gsi_qup_3 @ p 1 j @ : J S Z gsi_ssc_qup_0 @ 1 @ : ! " # $ % & ' ( J S Z SlimbusBSP qcom,smbus-controller _ jSLIMBUS v 0 LPASS @ 2 B dslimbus-default r x
sb_0_DeviceProps
0
sb_1_DeviceProps
0
sb_2_DeviceProps
0
sb_3_DeviceProps
0
sb_4_DeviceProps
0
sb_5_DeviceProps
sb_6_DeviceProps
slimbus_gen_config_1
%
6LPASS
D/vcs/vdd_lpi_cx
P
Z
m
|
w0
svs_npa_str
% 8 V m sbMmpmRegParam j slimbus , : sbLpmMmpmRegParam { slimbus , : kernel_test_devices@0 H n interrupt-controller@10140000 test,interrupt-control H I ^ @ device1@f101000 qcom,test,singleton oDevice region mapping with name H device1 )test_reg_singleton ] 4int1 device2@1011000 qcom,test,singleton ! oDevice region mapping with index device2 H ^ 4int2 device3@0 qcom,test,singleton oDevice with no region mapping device3 H _ 4int3 device4@1 qcom,test,not_compatible oDevice not compatible device4 H `
4zero int4 device5@1010000 qcom,test,non_singleton oDevice region mapping with name H device5 )test_reg_non_singleton sw @ C core boot mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config w debugtrace qcom,debugtrace debugtools version_tbl qcom,image_version_tbl_idx eic qcom,eic Z err_qdi
qcom,err_qdi P
pd_mon audio_process qcom,pd_mon_user_process_config
/ramfs/audio_lpai.mbn 3
%/rfs/root/vendor/firmware_mnt/image/audio_lpai.mbn
;audio_process
C
W
jaudio_pd charger_process qcom,pd_mon_user_process_config
%
;charger_process
C
W
jcharger_pd qsh_process qcom,pd_mon_user_process_config
/ramfs/qsh.mbn ,
%/rfs/root/vendor/firmware_mnt/image/qsh.mbn
;qsh_process
C
W
jsensor_pd ois_process qcom,pd_mon_user_process_config
/ramfs/ois_lpai.mbn ,
%/rfs/root/vendor/firmware_mnt/image/ois.mbn
;ois_process
C
W
jois_pd pd_mon_restart qcom,pd_mon_restart
y
rcinit qcom,rcinit_cfg rcinit_config_spinor
d
u0
( D ` | rcinit_config
!4
( D ` | tms_diag qcom,tms_diag 0 products pram_mgr qcom,pram_mgr SSC_PRAM pram_partition QMP QMP f SENSORS SENSORS f BUSES BUSES f GPI GPI f ( WIGIG WIGIG f BUSES_DEBUG BUSES_DEBUG f CAMERA_OIS CAMERA_OIS f SENSORS_OIS SENSORS_OIS f sdcloader qcom,sdcloader sdc_params < - ;a sdc_physpool E [ q'P systemcache qcom,systemcache-sw y @ - . llc-lpi-dump qcom,llc-lpi-dump J QSH_ISLAND_POOL SSC_ISLAND_POOL QSHTECH_ISLAND_POOL CAM_LLCC_ISLAND1_POOL diag qcom,adsp_core_diagcfg diagcfg_cmd * = ) U B Z _ z 0 D
a | " , F c! diagcfg_param x @ 8 L e
2 ) A Y @ p < ! A \ y K . H gd / O k @ < $ @Z \ zQURTOS_ISLAND_POOL QURTOS_ISLAND_POOL diagcfg_early_log _ diagcfg_f3_trace * qdsp_pm config qcom,config_data @ N g lpassRegRange s | f l2ConfigRegRange s | f cores-array core0 e > core1 f core2 g " core3 h core4 i core5 j X core6 l ! core7 m S core8 o . core9 { 2 core10 r + core11 v
/ core12 w ] core13 y 1 core14 z 0 core15 | n o 6 7 core16 j core17 m core18 k core19 l 5 memories-array memory0 memory1 clocks-array clock0 /clk/cpu clock1 lpass_core_cc_core_clk clock2 lpass_audio_cc_bus_clk clock3 lpass_aon_cc_aon_h_clk clock4 6 lpass_aon_cc_lpi_noc_ls_clk clock5 7 lpass_aon_cc_lpi_noc_hs_clk clock6 lpass_audio_cc_slimbus_core_clk clock7 lpass_core_cc_lpm_core_clk clock8 lpass_core_cc_lpm_mem0_core_clk clock9 lpass_audio_cc_codec_mem_clk clock10 lpass_audio_cc_codec_mem0_clk clock11 lpass_audio_cc_codec_mem1_clk clock12 lpass_audio_cc_codec_mem2_clk clock13 lpass_audio_cc_codec_mem3_clk clock14 lpass_aon_mx_cc_va_mem0_clk clock15 lpass_aon_mx_cc_va_mem1_clk clock16 $ lpass_core_cc_sysnoc_mport_core_clk clock17 lpass_audio_cc_bus_timeout_clk clock18 C ( lpass_aon_cc_lpass_0_lpmla_ahb_odsc_clk clock19 D ( lpass_aon_cc_lpass_1_lpmla_ahb_odsc_clk clock20 # lpass_core_cc_sysnoc_sway_core_clk clock21 ? scc_ccd_ahb2ahb_m_clk clock22 @ scc_ccd_ahb2ahb_s_clk clock23 A scc_ahb2ahb_s_clk clock24 B lpass_aon_mx_cc_ibi_clk clock25 S lpass_core_cc_resampler_clk clock26 X lpass_audio_cc_slimbus_clk clock27 Z lpass_core_cc_avsync_stc_clk clock28 [ lpass_core_cc_avsync_atime_clk clock29 ] lpass_core_cc_hw_af_clk clock30 ^ lpass_core_cc_hw_af_noc_clk clock31 n ! lpass_lpmla_cc_lpass_0_lpmla_clk clock32 o ! lpass_lpmla_cc_lpass_1_lpmla_clk clock33 t lpass_aon_cc_enpu_scheduler_clk clock34 j lpass_aon_cc_sdc_proc_fclk_clk clock35 m scc_ccd_clk clock36 l
scc_smem_clk busport-array busPort0 , 3 A N busPort1 @ , 3 A N busPort2 @ @ , 3 A N busPort3 A @ , 3 A N busPort4 B @ , 3 A N busPort5 C @ , 3 A N busPort6 D @ , 3 A N busPort7 , 3 A N busPort8 , 3 A N busPort9 , 3 A N busPort10 , 3 A N busPort11 @ , 3 A N busPort12 , 3 A N busPort13
, 3 A N busPort14 @ , ^ 3 A N busPort15 , 3 A N busPort16 @ , 3 A 1 N busPort17 @ , 3 A 1 N busPort18 , 3 A N busPort19 , 3 A N busPort20 , 3 Y N $ busPort21 , 3 Y N $ busPort22 , 3 Y N $ busPort23 , 3 Y N $ busPort24 ! , 3 Y N $ busPort25 " , 3 Y N $ busPort26 $ , 3 Y N $ busPort27 % , 3 Y N $ busPort28 ' , 3 Y ' N $ busPort29 ( , 3 Y N $ busPort30 + , 3 Y N $ busPort31 1 , 3 Y N $ busPort32 0 , 3 Y N $ busPort33 . , 3 Y N $ busPort34 2 , 3 Y N $ busPort35 / , 3 Y N $ busPort36 6 , 3 C Y N $ busPort37 7 , 3 D Y N $ busPort38 5 , l 3 Y N 5 busPort39 > , 3 Y N > extroute-array extBusRoute0 e p % extBusRoute1 e @ p ( extBusRoute2 e p % extBusRoute3 e A p ( extBusRoute4 e p % extBusRoute5 e B p ( extBusRoute6 e p % extBusRoute7 e C p ( extBusRoute8 e p % extBusRoute9 e D p ( mipsroute-array mipsBwRoute0 e p % mipsBwRoute1 e @ p ( pwrDomain-array pwrDomain0 z/core/cpu/latency pwrDomain1 ! zlpass_core_cc_lpass_core_hm_gdsc pwrDomain2 ! zlpass_aon_cc_lpass_audio_hm_gdsc pwrDomain3 z pwrDomain4 zlpass_aon_cc_lpass_ssc_gdsc cestaBw-array client0 lpass path0 5 cestaClk-array clk0 j lpass_aon_cc_sdc_proc_fclk_clk cestaPwrDomain-array pwrDomain0 zlpass_aon_cc_lpass_ssc_gdsc features-array feature0 a feature1 a feature2 a feature3 a feature4 a feature5 a feature6 a feature7 a feature8 a feature9 a feature10 a 5 feature11 a / feature12 a feature13 a feature14 a $=X feature15 a ' feature16 a feature17 a feature18 a feature19 a feature20 a feature21 a feature22 a feature23 a feature24 a feature25 a feature26 a feature27 a feature28 a feature29 a feature30 a feature31 a feature32 a feature33 a feature34 a feature35 a feature36 a feature37 a config_arch qcom,config_arch compensatedDdrBwTable 0 rp 0 0 ܓ X 0 t 2 0 U 2 0 % &6 0 , , s 0 3 2 0 : 8ـ 0 A > 0 H adspsnocVoteTable 8 ' 8 ' 8 ܓ X X ' 8 t 2 ' 8 U e ' 8 % &6 O ' 8 , , ' 8 3 2 ' 8 : 8ـ U ' 8 A > * ' 8 H ' compensatedLecDdrBwTable 0 X 0 2 0 0 ׄ s 0 e 0 % adspLecsnocVoteTable 8 X 8 2 8 O 8 ׄ 8 e U 8 % compensatedMlDdrBwTable 0 rp X 0 kI 0 Н 2 0 8 0 GW s 0 % n! 0 , adspMlsnocVoteTable 8 X 8 kI 8 Н 2 8 8 O 8 GW 8 % n! U 8 , adspToLpiNocFreqTable 0 $ $ ' 3
v =P 5 M O %bkP j mlToLpiNocFreqTable $ $ O ' RH
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